F84045 Asiliant Technologies, F84045 Datasheet - Page 12

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The CS4041 is the first product in the GreenCHIPS
CHIPSet product portfolio of Chips and Technologies,
Inc.
implementing a high performance, Energy Star
compliant 486 PC/AT design, while maintaining an
extremely competitive cost structure. The powerful
feature set includes the CHIPS "standard" system blocks
and offers a new level of system integration while
addressing the ever evolving requirements that the
market place demands. It is 100% PC/AT compatible
and directly supports the 486DX, 486DX2, 486DX4,
486SX and 486 derivatives that support the CPU write
back cache architecture.
The high performance CHIPSet consists of the F84041
Systems Controller and F84045 GreenCHIPS IPC. The
F84041 System Controller is packaged in a 208-pin
PQFP and integrates the major system logic functions.
Included in the F84041 is the CHIPS patented Page
Interleave DRAM controller, high performance cache
controller, VL local bus controller, ISA bus controller,
power management module, a local bus IDE controller
and fully compatible 8042 keyboard controller with
PS/2 mouse support. The companion F84045 is
packaged in a 100 pin PQFP and contains the industry
standard Integrated Peripheral Controller (IPC) which
includes the DMA controllers, timers, interrupt
controllers and real time clock.
The enhanced feature set of GreenCHIPS DRAM and
cache
Performance PC/AT designs. The page interleave
DRAM controller offers high performance as well as
extreme
subsystems. The DRAM controller supports up to eight
banks of memory that can be configured with 256K,
1M, 4M or 16M memory devices. Page interleaving,
timing modes, memory mix options, direct drive
support and block by block parity support can be tuned
to meet the most optimum requirements for the system
design. In addition, the high performance secondary
cache controller provides options that can be optimized
for performance, cost or both. The direct mapped cache
architecture employs internal comparators with external
TAG and data SRAM that can operate in a write-
through or write-back mode. Cache sizes from 64K to
1M are supported with flexible single bank or dual bank
support that allow flexible timing mode selection based
on CPU speed and SRAM speed.
Revision 1.0
controllers
It provides all of the system logic for
flexibility
2/10/95
are
in
perfect
supporting
for
Subject to change without notice
486
today's
1. Introduction
memory
High
11
The "Green" in GreenCHIPS comes from the Power
management support integrated in the CHIPSet. The
CS4041
management support for Energy Star compliant
desktops. Included in the power management section is
direct support for SMM operation and clock switching
for the popular 486 derivatives. Two event timers,
programmable I/O pins, I/O restart and programmable
event detection provide a wide range of options for
power management selection and customization.
The CS4041 provides new levels of integration in
system logic CHIPSets by providing a local bus IDE
interface and keyboard controller. The robust local bus
IDE interface is decoupled from the AT state machine
and does not use a VL local bus load. The interface is
versatile enough to support up to eight IDE drives
allowing each drive to have unique command settings.
The result is the best performance for each drive type
allowing significant performance gains over the
standard ISA interface. This is accomplished without
any compromise to the standard VL local bus.
1.1. CPUs Supported
1.2. External Chips
Qty
Intel 486 CPUs
AMD 486 CPUs
Cyrix 486 CPUs
IBM 486 CPUs
L1 (CPU) write back cache fully supported
SMI support (both Intel and Cyrix)
Clock Frequencies:
3
2
1
1
2
1
2
1
0
4
Add for Cache:
DRAM Buffers
Basic System
Add for IDE:
TTL Parts
provides
LS245
LS245
LS245
LS244
F244
F244
F244
F00
F08
25MHz, 33MHz, 40MHz, 50MHz
the
A <-> SA & LA
XD0:7 <-> SD0:7 & MA2:9 <->
SD8:15
Clock buffer
Miscellaneous
Cache address
BE# and W/R# combining
Data bus buffers
Control Signal Buffers
For 2 banks
For full complement of DRAMs.
Buffering based on loading.
perfect
Preliminary
Used For
level
Introduction
of
CS4041
power