F84045 Asiliant Technologies, F84045 Datasheet - Page 109

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

For example, if bank 2 contains 256K x 32 DRAM and bank 3 contains 1M x 32 DRAM and banks 0 and 1 are empty,
the starting address for bank 3 should be 0 and the starting address for bank 2 should be 4MB (4xxxxxh). A starting
address of 1xxxxxh for a 1M x 32 bank would be invalid (decoded as 0xxxxxh). To avoid holes or overlaps in the
bank decoding, largest banks should map lowest in the address space.
Interleave bit. The interleave bit is used for single-bank blocks only (RAS0-3). It causes an even numbered bank
(RAS0# or RAS2#) to map at even DRAM pages only, with twice the total block size. An odd numbered bank
(RAS1# or RAS3#) maps at odd DRAM pages only, also with twice the total block size. Thus, if two banks are both
the same size and have the same starting address, but one is odd and the other is even, turning on both interleave bits
allows two-way page-interleaving to occur between the two banks. Interleaving is discussed in more detail in the next
two sections.
If a block contains two banks (e.g., RAS0# and RAS4#), the two banks are page-interleaved automatically and the
interleave bit for that block should be zero.
DRAM depth. The DRAM depth bits define the type of DRAMs installed. This is a 3 bit field, in which the 000
setting disables the bank. The following are the allowable configurations:
5.10.1.1. Of Page Mode, Page Interleaving, and Single-RAS Active
This CHIPSet employs Page Mode, and Page Interleaving techniques. These are two different techniques, which may
be used independently or together.
Page Mode is always used in this CHIPSet for CPU accesses, both for bursts and between bursts. Page mode means
keeping RAS low while reading or writing multiple words within a DRAM page by providing only a new column
address and toggling CAS. A DRAM page is defined as a set of DRAM locations that can be addressed by changing
column address bits only. The locations in a page will be contiguous if the lowest CPU address bits map to the column
address, as is the case with the 4041. Address muxing is discussed further in Section 5.10.2.
Page Interleaving involves interleaving DRAM banks on a DRAM page boundary. This increases the percentage of
time that a page miss cycle will hit the opposite bank of DRAMs, hiding the RAS precharge of one bank while
accessing the opposite bank.
Single-RAS Active refers to allowing only one RAS# signal to be active at a time. With added CAS# pins (not
supported by the 4041), more than one RAS# potentially could be active at the same time, allowing DRAM bank
switching to occur without changing the state of the RAS# signals. Instead of just four CAS# signals, a fully general
four-bank multi-RAS active architecture would require 16 CAS# signals, four for each bank, and the performance
benefit would be minimal in systems that have both a CPU cache and a secondary cache. To conserve pins, the 4041
uses Single-RAS active only.
Revision 1.0
2/10/95
Table 5.19: DRAM Size Options
Prog bits
000
001
010
011
100
disabled
DRAM
depth
256K
16M
1M
4M
Subject to change without notice
256Kx1, 256Kx4, 256Kx16
1Mx1, 1Mx4, 1Mx16
4Mx1, 4Mx4
DRAM
16Mx1
types
108
block size
non-int
16M
64M
1M
4M
0K
Interleaved
block size
128M
32M
2M
8M
0K
Preliminary
Functional Description
CS4041