F84045 Asiliant Technologies, F84045 Datasheet - Page 38

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
10
11
Revision 1.0
Index
Index
10
11
1:0
2
3
4
5
6
7
0
1
2
3
5:4
6
7
dram timing
dram setup
Function
Function
Bits
DRAM Timing
clock mode, or 00h for 66.7 MHz CLKIN and 2X clock mode.
Read Timing Mode.
Read cycle RAS to CAS timing
(Reserved)
Write wait states, single write.
RAS Precharge Time.
Write burst Timing.
Refresh RAS pulse width.
DRAM Setup
0 and 1.
Interleave for bank 0. Should be zero if bank 4 is enabled.
If a bank is interleaved, i ts address range is doubled and it is active only when the interleave bit (A11
Interleave for bank 1. Should be zero if bank 5 is enabled.
Interleave for bank 2. Should be zero if bank 6 is enabled.
Interleave for bank 3. Should be zero if bank 7 is enabled.
(Reserved)
DRAM refresh enable.
Enable Local DRAM parity. 1=enabled. This bit provides an additional way to disable parity
2/10/95
or A12) compares. Banks 0 & 2 compare the interleave bit to a 0, and banks 1 & 3 compare it to
a 1. For proper interleaving, two banks must be the same size and have the same starting address.
See the text on interleaving for more information on what must be done to interleave properly.
checking over and above I/O Port 61. For parity checking to occur, both this bit and I/O Port 61
bit 2 must be enabled (a 0 for port 61). The NMI mask must also be set to send the NMI to the
CPU (I/O port 70 bit 7). For selective parity enabling by bank, see Index 1Dh.
En Loc Par dram refresh
00
01
10
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ref RAS
width
D7
D7
Description
3-2-2-2 page hits (default) . Valid in 2X clock mode only.
4-3-3-3 page hits
5-4-4-4 page hits (50MHz)
CAS generated 2 T states (1.5 for 3-2-2-2 mode) after RAS (default)
CAS generated 3 T states (2.5 for 3-2-2-2 mode) after RAS
1 wait state writes (3 T state minimum cycle)
2 wait state writes (4 T state minimum cycle)
2 T states of RAS precharge time.
3 T states of RAS precharge time.
-2-2-2 burst write timing (default)
-3-3-3 burst write timing
3 T states
4 T states (40MHz 80ns RAMs, 50MHz 70 & 80ns RAMs)
Do not interleave the bank
Interleave.
DRAM refresh disabled. ISA bus refresh handshaking may still occur.
DRAM refresh enabled.
write burst
Default = 00. Typical setting = C0h for no interleaving, or C3h to interleave banks
D6
D6
Default = 00. Typical setting for 70 ns DRAM = 01h for 33.3 MHz and 1X
Subject to change without notice
RAS prechg
ref rate
D5
D5
37
write ws
D4
D4
-
Int 3
D3
D3
-
RAS-CAS
Int 2
D2
D2
read burst1
Configuration Registers
Int 1
Preliminary
D1
D1
read burst0
Int 0
D0
D0
CS4041