F84045 Asiliant Technologies, F84045 Datasheet - Page 108

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Timing selections:
The DRAM controller is designed to support 4 double bank 36 bit SIMMs for a total of 8 banks. It will also support 9
bit SIMMs, and any combination of both. There are 4 DRAM blocks, each of which may contain 1 or 2 banks.
5.10.1. Block Decodes
Up to 8 banks of DRAMs are allowed. There are 8 RAS pins, one for each bank, and 4 CAS pins, one for each byte,
shared by all banks. The banks are grouped together into 4 DRAM "blocks".
Each DRAM block has the following programmable bits:
Starting Address. The Starting address provides the decode. A27 through A20 may be programmed. As the block
size gets bigger (as determined by the DRAM depth and a combination of the interleave bit and the number of banks)
successive lower bits in the starting address are ignored. The DRAM block must be placed on a block size boundary,
as shown in the following table:
Revision 1.0
Table 5.18: DRAM Block Starting Address
DRAM Depth
256K
256K
Optional DRAM data buffers.
CPU and alternate master timing modes may be set separately.
Support for CPUs with a write back cache
Support for SMM memory separate from user space.
Burst Reads: 3-2-2-2, 4-3-3-3, or 5-4-4-4 timing modes
Single writes: 1 or 2 wait state.
Burst Writes: 3-2-2-2, or 4-3-3-3.
RAS to CAS timing: 2 or 3 T states (1.5 or 2.5 for 3-2-2-2 burst reads).
RAS pulse width for refresh: 3 or 4 T states.
RAS precharge: 2 or 3 clocks
Starting Address (A27-20)
DRAM depth (none, 256K, 1M, 4M, or 16M)
Number of banks installed (1 or 2)
Interleave bit
2/10/95
16M
16M
1M
1M
4M
4M
Table 5.17
Block #
Block 0
Block 1
Block 2
Block 3
Interleave and number of banks
interleaved bank OR dual bank
non interleaved single bank
RAS and CAS usage
non interleaved
non interleaved
non interleaved
interleaved
interleaved
interleaved
one bank installed
Subject to change without notice
RAS used when
RAS0#
RAS1#
RAS2#
RAS3#
107
two banks installed
RASes used when
RAS0# & RAS4#
RAS1# & RAS5#
RAS2# & RAS6#
RAS3# & RAS7#
128M byte
16M byte
32M byte
64M byte
1M byte
2M byte
4M byte
8M byte
Size of
Bank
programmed
Address bits
A20-27
A21-27
A22-27
A23-27
A24-27
A25-27
A26-27
A27
CASes used:
CAS0-3#
CAS0-3#
CAS0-3#
CAS0-3#
Boundary size
Preliminary
Placement
Functional Description
128M
16M
32M
64M
1M
2M
4M
8M
CS4041