F84045 Asiliant Technologies, F84045 Datasheet - Page 19

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

2.4. 84041 Pin Descriptions
CLOCKs and RESET
CLKIN
CLK2OUT
SCLKOUT
SUSPA#
CPUCLK
STPCLK#
CLK2
SCLK
CWS#
BUSCLK
SYSRESET
Arbitration
HLDA
DGNT#
Revision 1.0
14
205
204
156
203
2
15
17
16
207
53
51
50
2/10/95
IN
OUT
OUT
IN
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
Input from Oscillator. Either 1x or 2x as determined by NMI at powerup (high for
2x system clock (when CLKIN is 2x). In full speed mode CLK2OUT is a buffered
The 1x system clock for everything except the CPU. This output buffered and fed
Suspend Acknowledge from the Cyrix CPU. May be left floating if not used.
1x CPU clock. This output is the same as SCLKOUT except that it may be stopped
Stop Clock signal to the CPU. Used for S series CPUs to stop the clock between the
2x clock input. Used for the DRAM state machine. It is also used as the source for
1x clock input.
Cache Write strobe. This is an advanced 1x clock used for the cache write strobe in
ISA bus clock. Generated by dividing the CLKIN pin down by a variety of factors.
System reset from the 4045.
CPU Hold Acknowledge. Whe n low, indicates that the CPU has control of the local
DMA controller grant. When low, indicates that either the DMA controller or an
1x, low for 2x).
BUSCLK. Also used as a time base for the power management timers.
version of CLKIN. In slow mode it is the output of the clock divider. When
CLKIN is 1x CLK2OUT will also be 1x, and will be at the same frequency and
phase as SCLKOUT. In either mode it has a very low skew with respect to
SCLKOUT and CPUCLK. It is externally fed back to CLK2 of the 4041, and
any other logic requiring a 2x clock.
back to SCLK of the 4041, goes to the 4045, and the VL-Bus. The unbuffered
SCLKOUT is used as CWS#.
Required only for Cyrix CPUs which contain a PLL. This pin is enabled with
Configuration Register 38h bit 2.
by the power management hardware.
CPU PLL and the CPU core. The 4041 will optionally drive this pin low before
changing clock frequencies.
the ISA bus clock divider.
order to meet the data hold time of the SRAMs. It is normally advanced by 3-
5nS from SCLK.
BUSCLK should be driven onto the ISA bus through a non-inverting buffer.
(BALE is generated during the low phase of BUSCLK).
bus. When high, either a local master, the DMA controller, or an ISA master has
the bus. The 4041 chip generates parity for DRAM write cycles when this pin is
high. Cache line fills are only done when HLDA is low. The DRAM controller
may switch timing modes based on HLDA to provide relaxed timing for
alternate masters.
ISA bus master has control of the bus. The 4041 becomes an ISA slave and
floats the ISA bus commands when this signal is low.
Subject to change without notice
Used to create CLK2OUT,
18
SCLKOUT and (optionally)
Preliminary
Pin Descriptions
CS4041