F84045 Asiliant Technologies, F84045 Datasheet - Page 136

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

When to Restart the Clock
The clock can only be restarted by a WakeB event. Normally an interrupt. Since software can't run when the CPU
clock is stopped, software obviously cannot restart the clock.
How to Stop the Clock
Two modes are available for clock stoppage. The first is to simply pull the STPCLK pin but leave the clock output
running. For an S series CPU this allows the clock to be restarted without having to wait for the VCO to stabilize. The
other method is to pull STPCLK and also gate off the clock. This is a lower power mode, but takes longer to restart if
the CPU contains a VCO (some do not, and may be restarted immediately). The CPU clock can also be stopped
immediately, without STPCLK#, if the CPU can tolerate it. Most CPU types either cannot tolerate a stopped clock at
all or require STPCLK# protocol.
Protocol for Changing the Clock Frequency
There are three protocol adjustments which can be made for changing the CPU clock frequency. They depend on the
requirements of the CPU in use.
The first is whether to assert STPCLK before changing the frequency. This is required for a CPU with a VCO (Intel S
series). It is not required for Cyrix or AMD, allowing clock switching to be instantaneous.
The second is whether to wait for STPACK (a special bus cycle) before changing the clock speed. Again, this is
required for a CPU with a VCO but not for others. Not all CPUs will give a STPCLK acknowledge. For Cyrix CPUs,
the SUSPA# signal may be used to indicate a stop clock acknowledge. This is required in Cyrix CPUs that have a PLL.
There is no need to wait for the SUSPA# signal on Cyrix CPUs without a PLL.
The third is how long to wait before releasing STPCLK after changing the frequency. Intel S series requires 1mS.
Non-VCO CPUs do not require any time.
Standard 486 CPU (SX, DX & DX2)
A standard 486 contains a PLL which requires the clock frequency to be changed slowly while it is operating. There is
no STPCLK# function or SMM capabilities. The minimum frequency is 8MHz. Two methods of power control may
be used:
Use a clock synthesizer to change frequencies. This requires a synthesizer chip which is capable of switching the clock
frequency slowly enough to satisfy the 486. Most do. A multifunction pin is used to control the frequency. The
internal clock divider is not used. Hardware clock switching is used.
Revision 1.0
WakeB
Pull STPCLK pin only
Pull STPCLK pin and gate off the CPU clock
Assert STPCLK before changing frequency: yes/no
Wait for STPACK before changing the clock: yes/no
Wait for x amount of time before releasing STPCLK: Yes/no & delay
2/10/95
Table 5.42: PLL Stabilization Delay Time
Subject to change without notice
Mode
000
001
010
011
100
101
110
111
135
No delay
125uS
250uS
500uS
Delay
32uS
64uS
1mS
2mS
Preliminary
Functional Description
CS4041