F84045 Asiliant Technologies, F84045 Datasheet - Page 131

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Time Base Selection (Index 8Ch). An approximately 1MHz clock is generated internally from the CLKIN pin, which
is first divided by 2 if 2x clock mode is selected. A 14.3 MHz clock source may also be used, which is provided on
either of two multifunction pins. Index 8Ch bit 3 selects between CLKIN (0) or 14 MHz (1). Index 8C bits 2:0 should
be set as shown in Table 5.34.1.
After selecting the time base, the slow clock divider should be set to produce the desired slow clock frequency. Since
many CPUs will not work below 8 MHz, this will be the most common mode. Suggested dividers are listed in Table
5.35.
In Tables 5.34.1 and 5.35, "CPU Frequency" refers to the CLKIN frequency in 1X clock mode, or CLKIN/2 in 2X
mode. The register settings are not affected by the 1X/2X clock mode.
Prescalers. The 1 s (approx.) time base is further divided by 64, then by 16 several times to produce the periods
below. Each timer may independently select one of these clock periods.
When an "Event" occurs the timer restarts to it's initial programmed value. "EventA" resets TimerA, while "EventB"
resets TimerB. The values may be read at any time by reading the 8 bit register. The initial value may be read by
turning off the timer, which is done by setting the count rate to 0. This both stops the clock and resets the value. When
Revision 1.0
Table 5.34.1: Time Base Selection
* The external frequency applied to the 14.3 MHz input pin need not be 14.3 MHz.
For other frequencies, the divider should be selected to achieve a period as close
to 1 s as possible.
Table 5.36: SMM Timer Resolutions and Max Time-Outs
2/10/95
8Ch Bit
Mode
3
0
0
0
0
1
0
1
2
3
4
5
6
Table 5.35: CPU Slow Clock Programming
CPU Frequency
33.3 MHz
25 MHz
40 MHz
50 MHz
14.31818 MHz Input*
67,108,864
4,194,304
Divider
CPU Frequency
262,144
16,384
33.3 MHz
25 MHz
40 MHz
50 MHz
1024
off
64
Subject to change without notice
8Ch Bits 6:4
Resolution (approx.).
001
010
010
011
64 seconds
4 seconds
256mS
16mS
64uS
1mS
--
8Ch Bits 2:0
130
Divider
000
001
010
011
100
2
4
4
6
(Timer disabled -- no timeout)
16mS (test mode)
256mS
4 seconds
64 seconds
1024 seconds (17 minutes)
16384 seconds (4.6 hours)
Resulting Slow Clock
Divider
Max time-out (approx.)
24
32
40
48
14
12.5 MHz
8.33 MHz
8.33 MHz
10 MHz
0.978 s*
Resulting
0.960 s
0.960 s
1.000 s
0.960 s
Period
Preliminary
Functional Description
CS4041