F84045 Asiliant Technologies, F84045 Datasheet - Page 155

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

6.9.2. Interrupt Controllers
The IPC contains two 8259-compatible interrupt controllers. The controller configured as the master is at IO ports 20h
and 21h, and accepts interrupts IRQ0:7. The controller configured as the slave is at IO ports A0h and A1h and accepts
interrupts IRQ8:15. What would be IRQ2 from the master controller actually receives the cascaded interrupt request
from the slave controller. The diagram below shows the basic hookup.
Revision 1.0
Driven directly by the SIPC:
Driven by the 4041 or externally pulled low:
Driven by external A:SA address buffers:
SA0:7
A8:9
A17:23
SA17:19 (optional)
A10:16 Driven by the 4041 using the value previously latched from the XD bus by SIPC LOUT.
A24:27 Driven low (000) by t he 4041.
A28:30 Pulled low (000) by external pull-down resistors. Not connected to either the SIPC or 4041.
A31
XA0:1 & A2:7 Driven by A:SA address buffers from SA0:7 (SIPC).
SA8:9
SA10:16
SA17:19
LA17:23
DMACLK
HOLD
DGNT#
AEN
SIPC LOUT
XD0:7
A0:7
DACK#
IOR#
MEMR#
MEMW#, IOR#
TC
Driven low by the 4041.
2/10/95
Driven by A:SA address buffers from A8:9 (SIPC).
Driven by A:SA address buffers from A10:16 (4041).
Driven by A:SA address buffers from A17:19 if not driven directly by SIPC.
Driven by A:SA address buffers from A17:23 (SIPC).
S0
Figure 6.3 DMA Cycle Timing
Subject to change without notice
S1
A10:16
S2
154
S3
SW
S4
Preliminary
Functional Description
CS4041