F84045 Asiliant Technologies, F84045 Datasheet - Page 145

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

To conserve battery power during standby mode, the 14 MHz clock does not run (14 MHz output is driven low
continuously) when PWRGOOD is low. There is a delay of about 250 ms from the rising edge of PWRGOOD to the
falling edge of SYSRESET to allow ample time for the 14 MHz oscillator to reach stable operation after PWRGOOD
goes high (as well as to allow a CPU internal VCO to stabilize.)
6.2.2. SCLK
SCLK, the 1x CPU clock, is provided to the SIPC. SCLK is used for the arbitration logic and (unless a 14.3 MHz
mode is selected) for generating the clock to the DMA controllers and ISA refresh logic.
6.2.3. DMA and Refresh clock generation.
The DMA controller and refresh clock (Index 0Ah) should be around 8 MHz. It is normally divided by 2 by the IPC
core (see Index 01h) to obtain the 4MHz at which the DMA controllers normally operate. Refer to Index register 0Ah
description for a list of available dividers and sources. The 14.3 MHz modes are available only in the 4045 and are
recommended for use when SCLK frequency is changed for power reduction.
6.2.4. 32.768KHz clock
Crystal pins are provided for the 32.768KHz clock. This clock is operating at all times, running off of the battery when
the power is off. It is used only by the real time clock portion of the IPC. The crystal frequency should be 32,768 Hz
(32x1024).
6.3. Reset
The SIPC contains the reset logic for the system. It receives PWRGOOD and generates SYSRESET and CPURESET
in response to PWRGOOD going high. It also receives soft reset requests over the control link or Port 92h to generate
CPURESET.
PWRGOOD disables all outputs and gates off all inputs to the chip except for PSRSTB, the 32KHz oscillator pins, and
of course PWRGOOD itself. Also, the 14.3MHz output is driven low rather than floated. When PWRGOOD goes
high the outputs are enabled. SYSRESET and CPURESET are driven high, and remain high for approximately 8
million SCLKs (250 ms if SCLK is 33.3 MHz) to assure proper startup of the 14.31818 MHz oscillator, and to allow
the 486 internal VCO to stabilize.
The 1x clock is expected to be in the same phase as the 486, which is high for phase 1 and low for phase 2. The resets
will be generated on the rising edge of SCLK.
SYSRESET is generated based on the PWRGOOD circuit alone. CPURESET is generated based on PWRGOOD, but
is also be generated for "soft resets". The following are the sources of soft resets:
Keyboard Reset and Shutdown are sent to the SIPC through the control link from the 4041. When the SIPC receives
the request, it immediately passes the request on to the logic which arbitrates CPURESET with CPU HOLD.
Port 92h is contained in the SIPC. When bit 0 makes a 0 to 1 transition, a CPU reset is requested after a delay of about
16 cycles of the 4045 internal BUSCLK (Index 0Ah). This delay allows the CPU to execute a HALT instruction
following the output to port 92h.
Revision 1.0
Keyboard controller reset
CPU shutdown cycle
Port 92h bit 0 transitioning from a 0 to a 1.
2/10/95
Subject to change without notice
144
Preliminary
Functional Description
CS4041