F84045 Asiliant Technologies, F84045 Datasheet - Page 126

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The "GPin data" reads the current level of the pins listed. These pins may be read regardless of the function selected
for that pin.
5.14. Power Management
Power management consists of the following features:
5.14.1. Power Management Techniques
CS4041 supports control of system power through the following chipset output signals:
Revision 1.0
CPU clock. The CPU clock can be slowed or stopped, either by software command (Index 8Eh) or automatically
due to system inactivity (see Timers A and B below). In addition, execution of a HALT instruction can cause the
CPU clock to be stopped, either unconditionally or only if running slow (Index 8Dh). While running slow, the
clock can switch back to full speed automatically via a "Wake A" event (Indexes 82h and 83h) or by software
command (Index 8Eh). While stopped, the clock can start running again automatically in response to a "Wake B"
event (Index 85h). Timer A and Wake A are associated with clock slowing, while Timer B and Wake B are
associated with clock stopping and restarting. Index 8Ch determines the CPU clock speed for slow mode. CPU
clock slowing or stopping can be done instantaneously or using #STPCLK protocol with the CPU, or using the
STPCLK# output to control an external clock generator chip. The clock switching protocol is selected via Index
8Dh.
CPU SMI pin. Any one of a wide range of selectable hardware events can cause a System Management Interrupt
(SMI). SMM software (System Management Mode) can then decide what further action to take, if any. An SMI
can also be triggered directly by a software command (Index 8Eh). Indexes 92h and 93h determine which events
can cause an SMI. Indexes 90h and 91h indicate which enabled SMI events are currently pending. Software can
selectively clear pending event indicators by writing to Indexes 90h and 91h. One possible SMI event is I/O restart.
Index 95h determines which I/O ranges cause an I/O restart SMI. Index 94h allows SMM operation to be adjusted
according to the CPU type. As explained in Section 5.6, the 4041 can set aside DRAM space specifically for SMM
(Indexes 1Ch and 1Dh). The SMIACT# / SMIADS# signal from the CPU is used to ascertain whether or not SMM
is currently in effect.
Ability to select the speed of the system clock under software or hardware control
Ability to restart I/O inst ructions.
Ability to detect inactivity in the system using two activity timers, and then:
Ability to detect a HALT cycle in the system and either:
Ability to detect a wake up event and:
Ability to have a separate memory area for SMM code and data.
Ability to access all system resources from within SMM.
Ability to redirect CPU soft resets to SMM.
2/10/95
Generate an SMI (either timer)
Switch to the slow clock (Timer A)
Stop the CPU clock (Timer B)
Generate an SMI
Stop the CPU clock.
Generate an SMI (either event).
Switch to full speed mode (Wake A event)
Restart the clock (Wake B event).
Subject to change without notice
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Preliminary
Functional Description
CS4041