F84045 Asiliant Technologies, F84045 Datasheet - Page 132

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

reading the count while the timer is active, it is possible to read it while it is de-incrementing. Reading it multiple times
until the same value is read twice in a row is advisable to guarantee an accurate value.
The timers and associated dividers are clocked approximately once every 16 uS if the proper time base dividers are set.
Loading the timers with a new value also occurs only on these clock edges. With the synchronization required, after
writing a new timer value it will take between 8 and 24 uS before the new value is loaded into the timer. Reading the
timer before this occurs will give the old value. It is also possible for the timer to time out and cause an SMI or clock
slowdown up to 24 uS after the timer is reset or an event occurs.
The timers are reset on any combination of the following:
See the Events Detection section below on how these events are actually detected, and what I/O ports, etc. are used.
5.14.5. Wake Up Events
There are two programmable wake up events. WakeA is normally used to switch back to full speed mode. WakeB is
normally used to start the CPU clock after it has been stopped. Each may also generate an SMI.
5.14.6. Events Detection
There are 4 "Events" which do various functions. Two of them reset the activity timers while the other two wake up
the system from slow or stopped clock. The functions are:
EventA and Wakeup A have individual control for almost every possible event. They are programmable separately for
maximum flexibility. EventB and Wakeup B require far less flexibility. They provide only a few possible key event
selections, but may also select EventA or Wakeup A as one of their sources, effectively taking the "A" selection and
adding to it.
EventB will generally use EventA, and add IRQ0 to it. If used, it generally times the active period of the timer tick
interrupt.
Wakeup B restarts the CPU clock. INTR, NMI, and external events are all that are generally required. A stopped clock
CPU is not able to access any I/O ports or generate any INTA cycles (for individual IRQ detection by the 4041) or
assert HLDA.
The following explains how each event is detected.
INTR. INTR is generated by the 4045, but it is monitored by the 4041 on a dedicated 4041 input pin. In the 4041,
INTR is used solely for event detection. It is generally used as a Wakeup B event, which re-enables a stopped clock.
When this pin is high it causes an event, and continues to do so as long as it is high.
Revision 1.0
INTR or NMI signal to the CPU.
Interrupts (IRQ0, IRQ1, IRQ3,4,5,7, IRQ6,14, IRQ9,13, IRQ,8,10,11,12,15)
I/O port accesses (Floppy, IDE1, COM1&2, COM3&4, LPT1,2,3, KB, programmable1,2)
Video Memory access.
HLDA going high (alternate master active).
An external pin going active.
2/10/95
Table 5.37: Event Functions
Event Name
Wakeup A
Wakeup B
EventA
EventB
Subject to change without notice
Switch back to full speed
Restart the CPU clock if
Reset TimerA
Reset TimerB
Function
stopped
131
Additional Function
Generate an SMI
Generate an SMI
Preliminary
Functional Description
CS4041