F84045 Asiliant Technologies, F84045 Datasheet - Page 3

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

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Revision 1.0
Local Bus
DRAM Controller
Cache Controller
- VESA Local Bus 2.0 Compatible
- Full L1 Write Back Cache Support
- Up to 3 LDEV#s and 3 sets of LREQ# / LGNT#
- Read and write bursting from VL Masters
- 8 banks of DRAMs supported (4 double banks
- Page mode and page interleave
- 256K, 1M, 4M, and 16M deep DRAMs
- Direct Drive RAS
- Direct drive CAS, DWE, and MA for up to 36
- Hidden refresh with staggered RAS
- SMM memory support
- Variety of timing modes for system optimization
- Direct mapped, external tag, internal comparator
- 16 byte line size
- 64K,
- Write back or Write through
pairs provided directly
supported
SIMMs, etc.)
supported
DRAM chips
128K,
2/10/95
256K,
D0:31
A2:31
Cache
Control, status
512K
Keyboard
Mouse
Figure 1: System Block Diagram
Subject to change without notice
EPROM
or
DRAM
CS4041 CHIPSet
1M
Tag
size
4041
DRAM
Cache
ISA
CTRL
4045
SIPC
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Power Management
Integrated Local Bus IDE
Keyboard Controller
RAS
CAS
XD0:7
- Single bank or dual bank (word interleaved)
- Multiple timing modes supported for cost
- SMI support
- Many power management features can be
- Internal Clock switching and stopping
- Intel, AMD, and Cyrix support
- Event monitoring
- I/O restart capability
- Requires only 3 TTL
- Support for 8 drives (4 connectors)
- Data port accesses accelerated via local bus
- Timing modes selectable for each drive
- Integrated
- Mouse port included
- Keylock input provided on a multifunction pin
SD0:7
A8:9
SA17:19
A17:23
cache
performance tradeoff
utilized without SMI
accesses
controller
MA0:11
Interrupts, DMA
244
245
245
245
245
245
245
245
state
Optional
D0:7
SD8:15
ISA commands
SD0:7
SD8:15
SA16, LA16:23
SA0:7
SA8:15
SA17:19
machine
Preliminary
Local Bus
IDE
based
Bus
ISA
keyboard
CS4041