F84045 Asiliant Technologies, F84045 Datasheet - Page 127

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

CS4041 also supports system power management through the following input signals:
The 4041 provides two programmable timers that can be used to detect system inactivity and either generate an SMI or
automatically slow or stop the CPU clock. The timers are clocked at a base rate determined by Index 8Ch bits 0:3,
intended to be set as close to 1 s as possible.
Revision 1.0
General Purpose Outputs. A total of six output pins are potentially usable as general purpose programmable
outputs, under direct software control. Depending on the specific system objectives, some or all of these signals
could be used to switch power on or off to various parts of the system. The pins available for general purpose
outputs are GPB, GPC, GPD, RAS6#, RAS7#, and FLUSH#. All six pins also have other possible functions, as
programmed by Indexes 3Ch and 3Dh (also 3Eh bits 7:6). When used as general purpose outputs, Index 3Eh bits
0:5 define the output pin states.
Note: All six general purpose outputs default to the high state immediately following system reset (SYSRESET#),
but will not necessarily remain high unless appropriately programmed by the BIOS. Several of the signals default
to DRAM related functions and should be programmed by the BIOS as needed prior to performing the first DRAM
access. GPC defaults to WPROT#, which will go low with the first ROM access in the 0Fxxxxh range. If GPC
needs to remain high in the intended system implementation, BIOS should reprogram it as IOCS0# before executing
the initial far jump to the 0Fxxxxh area. This can be accomplished either by placing the necessary instructions in
the FFFFFFFxh area prior to the far jump, or by executing a NEAR jump to the GPC instructions, followed by the
far jump.
EXT0 input. This is a multifunction pin (GPA) whose function is controlled by Index 3Ch. If used as EXT0, this
input can be programmed to cause an SMI and/or affect CPU clock speed. EXT0 can be edge or level triggered
(Index 8Fh). Alternatively, this pin can be used as a general-purpose input, directly readable by software via Index
3Fh.
EXT1 input. This is a multifunction pin (LDEV2#) whose function is controlled by Index 3Ch. If used as EXT1,
this input can be programmed to cause an SMI and/or affect stopping and restarting of the CPU clock. EXT1 can be
edge or level triggered (Index 8Fh). Alternatively, this pin can be used as a general-purpose input, directly readable
by software via Index 3Fh.
Other General Purpose inputs. LDEV1, MCLK, and MDATA can all be used as general-purpose inputs, directly
readable by software via Index 3Fh. These are all multifunction pins whose functions are selected by Index 3Ch.
Timer A can detect system inactivity and automatically switch the CPU clock to slow mode and/or generate an
SMI. The timer is initialized by software and can be re-initialized to the same timeout value by any of a large set of
possible hardware events as selected by Indexes 80h and 81h ("Event A"). If none of the enabled events occur
within the programmed timeout interval, Timer A times out and causes an SMI and/or CPU clock speed reduction.
Another set of possible events, "Wake A" (Indexes 82h and 83h), can automatically restore the CPU clock to full
speed and/or generate an SMI. The timeout interval is programmed via Indexes 88h (prescaler) and 89h. For
highest resolution in Index 89h, the prescaler should be set to the fastest rate that allows the desired timeout interval
to be programmed in Index 89h.
Timer B can detect system inactivity and automatically stop the CPU clock or cause an SMI. The timer is initialized
by software and can be re-initialized to the same timeout value by any of a large number of possible hardware
events as selected by Index 84h ("Event B"). If none of the enabled events occur within the programmed timeout
interval, Timer B times out and causes an SMI or CPU clock stop. Another set of possible events, "Wake B" (Index
85h), can automatically restart the CPU clock to whatever speed was last selected, and optionally cause an SMI as
well. The timeout interval is programmed via Indexes 8Ah (prescaler) and 8Bh. For highest resolution in Index
8Bh, the prescaler should be set to the fastest rate that allows the desired timeout interval to be programmed in
Index 8Bh.
2/10/95
Subject to change without notice
126
Preliminary
Functional Description
CS4041