F84045 Asiliant Technologies, F84045 Datasheet - Page 150

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Subject to change without notice
Functional Description
6.5.3.5. WBACK# Signal
The WBACK# will remove the CPU hold, without going through any arbitration. The LGNT# or DGNT# (which ever
is active) will remain active at this time, even though HOLD and HLDA go inactive. A CPU with a write back cache
will pull WBACK# low in the middle of a DMA, ISA Master, or local master bus cycle to allow the CPU to perform a
write back cycle. Whatever master has control of the bus when the WBACK# signal is activated will retain control
until after WBACK# goes inactive.
There are two timing modes for this. The first is the 4035 mode, which keeps HOLD low as long as WBACK# is low.
This mode is not particularly useful, but is included for historical reasons. The WBACK# pin was actually listed as
reserved on the 4035. The second mode keeps HOLD low for only 4 T-states, then takes it back high. This allows the
CPU to come out of HOLD only long enough to do the write back cycle (it will not go back into HOLD until it is
finished). The timing is shown below:
WBACK#
HOLD
A8:9, 17:23
(A8:9, and A17:23 are driven during DMA cycles only)
Figure 6.1 WBACK# Timing
If the DMA controller has the bus, the SIPC floats A8:9 and A17:23 when WBACK# is active (WBACK# is clocked
internally first). WBACK# should be connected to the 4041 WBACK# output pin.
6.5.3.6. Arbitration Lock
This applies to the 4045 only. The arbitration lock is for the S series CPU. When the frequency is changed the CPU
will not respond to EADS# cycles properly until the internal VCO has stabilized. Software will set the arbitration lock,
switch the frequency, then release the lock after the VCO stabilizes.
When register 0B bit 0 is set to a 1, HOLD will not go high. If it is already high it will not be affected.
Software Caution: When register 0B bit 0 is a 1 and register 0C bit 3 is set to a 1, if a CPU restart is attempted by
actually resetting the CPU, the CPU reset will NOT occur until one of these bits is set to a 0. The CPU reset will be
waiting for the CPU to go into HOLD, but HOLD will be blocked. This situation should never occur in normal
operation.
6.5.3.7. Misbehaved ISA master fix
Some ISA masters do not take MASTER# high until DACKn# goes high. The round trip time for this, and the fact that
MASTER# is open collector (and rises slowly) can cause the A to SA/LA buffers to be still turned around when the
CPU begins its next cycle. The 4045 (unlike the 4035) prevents the CPU or VL master from getting control until a
minimum of 90 ns (3 T-states) after MASTER# goes high.
Revision 1.0
2/10/95
149
Preliminary
CS4041