F84045 Asiliant Technologies, F84045 Datasheet - Page 66

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
09
Revision 1.0
index
09
0
1
2
3
4
5
6
7
function
misc
Bits
4045 Misc Control
for internal controller.
Deturbo (Performance Control Enable).
Preemptive protocol for LGNT#.
Refresh Request Enable. This bit blocks the Timer 1 Refresh request when disabled. This prevents
ISA bus refresh enable.
A20M# / TEST# and 4045 LOUT pin enable function.
GATEA20 emulation disable.
Keyboard interrupt mode.
Floating point error mode.
2/10/95
Register 08h, and has nothing to do with the slow CPU clock mode. This bit is ORed with the
invert of the Turbo Switch (SLOW# input pin).
reset problems, which may occur when a refresh request is generated during the reset sequence.
The 8254 timing is not disabled at reset.
4041 LIN should be enabled (Index 39h bit 1) before setting this bit to 1.
fpintmode
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D7
Description
Normal mode (default)
Performance Control Enabled.
Non-preemptive protocol.
Preemptive protocol. The arbitration logic will take LGNT# low when the DMA
Block the Timer 1 refresh requests.
Enable Timer 1 refresh requests. (Essential for DRAM refresh.)
Disable ISA bus refreshes. The Refresh request is still sent to the 4041 or 4031, and
Enable ISA bus refresh. Needed for full ISA compatibility .
The A20M# / TEST# pin is an input, forcing the 4045 into test mode when it is low.
The A20M# / TEST# pin is an output, driving A20M#. The test mode is disabled.
The A20M# pin is only the Port 92 GATEA20 signal (which is low after reset).
The A20M# pin is the OR of the Port 92 GATEA20 and the emulated 8042
IRQ1 is received on the pin directly (from external 8042).
IRQ1 is received over the control link from the 4041 (internal KBC).
Internal (486) mode. FERR# and IGNNE# pins are provided. IRQ13 is generated
External mode. IRQ13 and I NTCLR pins are provided. The remainder of the logic
kbintmode
LREQ# has gone inactive (default).
controller requests the bus. It will wait for LREQ# to go inactive before granting
the bus to the DMA controller. This is VL-Bus compatible.
Master Refresh cycles are still performed. Disabling ISA refresh may allow a
TTL chip to be deleted in systems that don't need ISA refresh.
The 4045 LOUT pin is also floated to allow the 4041 LIN pin to be used for the
test mode control on the 4041. (Default).
The 4045 LOUT pin is driven.
(default).
GATEA20 information received across the control link.
internally (default).
is provided externally. This mode is used where a pin for IRQ13 is required
(such as a system with a Weitek Coprocessor).
D6
Subject to change without notice
Default = 00. Typical setting = 3Ch for external keyboard controller, 7Ch
8042em
D5
ga20/test
65
D4
This enables the performance control programmed in
The arbitration will not take LGNT# inactive until
ISA ref
D3
ref en
D2
lbm proto
Configuration Registers
Preliminary
D1
Deturbo
D0
CS4041