F84045 Asiliant Technologies, F84045 Datasheet - Page 81

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Chip Select or Strobe
When Chip Select is selected, the decode is an asynchronous decode of the address and will be setup to and held after
IOR# and IOW#. It acts differently depending on the current bus master:
When Strobe is selected, the decode is ANDed with the IOR#, and IOW# strobes (as determined by the read and write
activation bits). This allows the pin to be connected to a latch gate or clock, or to a three state buffer enable.
This bit allows the decode to be disabled during ISA bus master cycles.
5.5.2. Memory Addressing
The default for memory cycles is the ISA bus, but most get claimed by the internal DRAM/Cache controller. Memory
decodes in the 4041 include the following:
DRAM Block Decodes. These are explained more fully in the DRAM controller section. Each block has a starting
address, DRAM size, and number of banks installed (1 or 2) bit. This is the same as the CS4021 and CS4031 (the
CS4031 always had 1 bank per block).
640K to 1M Shadow RAM . Each of the following memory ranges has a separate shadow RAM bit for reads and
writes. If the bit is a 0 the access goes to the ISA bus, ignoring the DRAM bank decodes. If the bit is a 1, the access
goes to the DRAM (assuming there is DRAM present there, which there always is in a normal system). The D0000,
E0000, and F0000 have separate shadow enable bits for user mode and SMM mode. This allows SMM memory to
appear only in SMM mode.
Revision 1.0
Disabled or Enabled During ISA Master Accesses
CPU or VL master: M / IO# is decoded alone with W / R# (according to the read and write activation bits).
ISA master: The cycle type (memory or I/O, read or write) cannot be determined until the strobe goes active.
If only one of the read and write activation bits are set, the output ANDed with it and will act the same as in
the strobe mode. If both are active, it will be an asynchronous decode of the address (and will be active for
memory cycles also).
DRAM block decodes
640K-1M shadow bits
Programmable memory decodes
SMM memory decode.
Cache test window.
C0000-C3FFF (VGA BIOS area)
C4000-C7FFF (VGA BIOS extension)
C8000-CBFFF (adapter board BIOS area)
CC000-CFFFF (adapter board BIOS area)
D0000-DFFFF (miscellaneous)
E0000-FFFFF (System BIOS extension)
F0000-FFFFF (System BIOS)
Index CS0
2A
2B
28
29
2/10/95
Index CS1
2C
2D
2E
2F
mask15:11
cs/stb
A15
D7
A7
Subject to change without notice
mask10
master
A14
D6
A6
I/O writes
mask9
A13
D5
A5
80
I/O reads
mask8
A12
D4
A4
mask7
local
A11
D3
A3
size2
A10
D2
A2
-
size1
Preliminary
Functional Description
D1
A1
A9
-
size0
D0
A0
A8
-
CS4041