F84045 Asiliant Technologies, F84045 Datasheet - Page 86

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.6.2. Additional 4041 SMM Features
5.6.2.1. Flush CPU Cache on SMM Entry
The 4041 may optionally flush the CPU cache upon entry into SMM mode. It does this by driving FLUSH# low for 4
clock cycles when SMIACT# goes active (a high to low transition). This function is not supported (and is not needed)
for CPUs that use SMIADS# instead of SMIACT#. This function is generally not required in any case.
The 4041 has no mechanism to flush the CPU cache upon exit from SMM mode, or to flush the secondary cache. No
cache flushing should be needed in connection with SMM in any case if SMM space is allocated in shadow RAM as
described in Section 5.6.1. Cache flushing considerations are discussed further in the next section.
5.6.2.2. SMM Caching and Cache Flushing
SMM memory may be optionally cached in the L1 cache. Index 94h bit 3 determines whether it is cached.
SMM memory cacheability in L2 cache can be controlled via Index 18h, bit 3, assuming SMM memory is in shadow
RAM (as it normally will be). This bit controls L2 cacheability of the entire shadow RAM area from 0A0000h through
0FFFFFh, including the system BIOS area (assuming system BIOS is in shadow RAM, as it normally will be).
When deciding where to place SMM code and whether or not to make it cacheable, the potential need for cache
flushing in connection with SMM should be considered. Flushing a writeback cache, in particular, can be extremely
time consuming because of the potentially large number of “dirty” cache lines that might need to be written back to
memory. L1 and L2 cache flushing in connection with SMM becomes necessary in two main cases (see also section
5.9.4):
(a)
(b)
No cache flushing is needed if the address range always maps to the same target memory area in both SMM and user
mode, or if the address range is non-cacheable in both SMM and user mode.
Case (a) above should never arise in a CS4041 system if SMM code and data reside in shadow RAM as described in
section 5.6.1. There is no way for the SMM address range to map to local DRAM (other than SMM space) during user
mode. At most, the SMM address range might map to ISA bus memory or ROM during user mode. The SMM address
range will automatically either be non-cacheable during user mode because it doesn’t map to local DRAM, or will
remain mapped to the SMM space.
Case (b) above can arise if the address range used for SMM maps to ISA bus memory or ROM during user mode. For
example, 0Dxxxxh could be used for SMM space and also for user mode option ROMs. In that case, SMM space
should be made non-cacheable in both L1 and L2 caches in order to avoid the need for cache flushing per case (b)
above. SMM non-cacheability can be achieved by setting Index 18h bits 3:2 to ‘10’ and setting Index 94h bit 3 to ‘1’.
These settings allow other shadow RAM areas, such as system and video BIOSes, to remain cacheable in L1 cache.
Revision 1.0
Entering SMM. If SMM address space is cacheable in user mode and is mapped to a different area of DRAM
during SMM, then cache flushing is necessary upon entry into SMM to prevent unwanted cache hits during
subsequent SMM accesses.
Exit from SMM. If SMM address space is cacheable in SMM mode and is mapped to a different target area
(e.g., DRAM or ISA bus) during user mode, then cache flushing is necessary upon exit from SMM to prevent
unwanted cache hits during subsequent user mode accesses to the same address range.
2/10/95
Subject to change without notice
85
Preliminary
Functional Description
CS4041