F84045 Asiliant Technologies, F84045 Datasheet - Page 156

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

In a PC/AT the interrupt controllers are programmed in edge triggered mode. This means an enabled IRQ flows
through to INTR transparently until INTA occurs, but is latched by INTA. For proper recognition, an IRQ must remain
asserted until after the corresponding INTA has occurred. The interrupt base for the master controller is 08 (yielding
vectors 08-0F during INTA cycles) while the slave controller is set to 70h (yielding vectors 70h-77h). Windows
reprograms them to 50h and 58h respectively. Other operating systems may put them at different places.
6.9.3. Timers
The IPC contains an 8254 compatible 3 channel timer. All three timer channels run off of a 1.19 MHz clock (14.31818
MHz divided by 12). The timers are used as follows:
Revision 1.0
Table 6.1 Timer usage and setup
Timer
0
1
2
2/10/95
Figure 6.4 Interrupt Controller Internal Connections
Periodic Interrupt
IRQ0 (Timer)
IRQ1 (Keyboard)
IRQ3 (ISA bus)
IRQ4 (ISA bus)
IRQ5 (ISA bus)
IRQ6 (ISA bus)
IRQ7 (ISA bus)
CS# 20 & 21
IRQ8 (RTC)
IRQ9 (ISA bus)
IRQ10 (ISA bus)
IRQ11 (ISA bus)
IRQ12 (ISA bus)
IRQ13 (FPU)
IRQ14 (ISA bus)
IRQ15 (ISA bus)
INTA#
XA0
CS# A0 & A1
IOR#
IOW#
Speaker
Refresh
Usage
Subject to change without notice
Various (Generally Square Wave)
vcc
SP/EN
SP/EN
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
INTA
A0
CS
RD
WR
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
INTA
A0
CS
RD
WR
Square Wave (mode 3)
8259
8259
155
Pulse (mode 2)
CAS0
CAS1
CAS2
CAS0
CAS1
CAS2
INT
D0
D1
D2
D3
D4
D5
D6
D7
INT
D0
D1
D2
D3
D4
D5
D6
D7
Mode
INTR to CPU
XD0:7
0000 (65536)
0012h (18)
Various
Divider
Preliminary
Functional Description
CS4041