F84045 Asiliant Technologies, F84045 Datasheet - Page 46

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
2B
2C
2D
2E
2F
30
31
Revision 1.0
2:0
3
4
5
6
7
7:0
7:0
Index cs0 Index cs1
2A
2B
28
29
Bits
I/O Decode #0 Configuration.
to enable a strobed chip select for I/O read and write, or 08h to enable LDEV# internally for a local
bus slave that doesn't provide an LDEV# signal.
(Reserved)
Local bus I/O range. 1= forces the LOC AL# function for the range
Activate Chip Select for I/O reads. 0= don't activate, 1= activate. See note in text on limitation.
Activate Chip Select for I/O writes. 0= don't activate, 1= activate. See note in text on limitation.
Allow Chip Select for ISA Master accesses. 0= disable for master, 1=allow for master.
Chip select or strobe.
I/O Decode #1 Address Low.
I/O Decode #1 Address High.
I/O Decode #1 Size and Mask.
I/O Decode #1 Configuration.
See CS0 for descriptions of the bits.
Memory Decode #0 Address Low.
disabled.
Address bits 23:16
Memory Decode #0 Address High
disabled.
Address bits 31:24
2/10/95
2C
2D
2E
2F
0
1
mask/size mask15:11
add high
function
add low
config
Description
CS0 acts as a chip select decoded from CPU address and M/IO# only
CS0 is ANDed with the read and/or write strobe.
cs/stb
A15
D7
A7
Subject to change without notice
mask10
master
A14
D6
A6
Default = 00.
I/O writes
Default = 00.
Default = 00. Typical settings: 00h to disable Decode #0, B0h
Default = 00. To disable Decode #1, use 00h.
mask9
Default = 00.
A13
D5
A5
45
Default = 00. Typical setting = FFh if Decode #0 is
Default = 00. Typical setting = FFh if Decode #0 is
I/O reads
mask8
A12
D4
A4
mask7
local
A11
D3
A3
size2
A10
D2
A2
-
Configuration Registers
Preliminary
size1
D1
A1
A9
-
size0
D0
A0
A8
-
CS4041