F84045 Asiliant Technologies, F84045 Datasheet - Page 144

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

6.1.2. Using 4045 in place of 4035
The 4045 is a pin-for-pin drop-in replacement for the 4035. The 4045 powers up as a 4035, allowing it to function
exactly as a 4035. There are a few board and system level considerations to make sure that none of the 4045 extended
features are accidentally enabled in a 4035 environment.
6.1.3. A quick design checklist.
The following system level functions are required for proper 4045 operation.
6.2. Clocks
Three clock frequencies are used in the SIPC:
6.2.1. 14.31818 MHz clock
Crystal pins are provided for a 14.31818 MHz clock. 20pF capacitors should be included from each crystal pin to
ground as well as a 10M resistor across the crystal pins. X2 should be buffered with a bus driver or inverter to form
OSC for the ISA bus. A 33 ohm series resistor should be provided between the buffer and the bus, close to the buffer.
The 14.31818 MHz clock is divided by 12 internally to form the 1.19MHz clock used by the IPC timers.
Revision 1.0
The DGNT# pin should have a pull-up resistor on it, since one of the superset options (SA17:19 redefinition)
may be essential for ROM access at power up and is based on the state of the DGNT# pin when SYSRESET
goes low. A 10K pull-up is sufficient.
Index register 09h bit 3 should be set to a 1 to assure that ISA refresh is enabled. For the 4035, this bit is
described as "Reserved, write as 0."
Index registers 0Bh and 0Ch should be left in their default states. They power up to 0s, in which all
functions are 4035 compatible. These registers do not exist in the 4035.
VCC must be supplied from a battery backed up circuit in order for the Real Time clock and CMOS RAM to
operate when the power is off. There are no separate power pins for these. The circuit that switches between
battery and main +5V must be capable of delivering normal operating currents to the 4045 during normal
operation without excessive voltage drop. Refer to the Application Schematic Examples for a suggested
circuit.
DGNT# must have either a pull-up or pull-down resistor in order to set the mode of the SA17:19 pins at reset.
A pull-up selects SA17:19 while a pull-down selects the additional VL bus arbitration signals and the 16-bit
I/O chip select input. DGNT# is floated while SYSRESET is high and sampled on the falling edge of
SYSRESET.
A20M# should have a pull-up resistor. 10K is sufficient. After reset A20M# is the TEST input pin. A
configuration register bit enables the A20M# output driver. The pull-up is required both to prevent the SIPC
from going into a test mode and to allow the CPU to boot properly (A20M# held high).
LOUT should have a pull-up. LOUT is floated at reset because it connects to 4041 LIN, and 4041 LIN is the
TEST pin on the 4031 and 4041. The same configuration register bit that enables A20M# also enables LOUT.
14.31818MHz for the timer functions
SCLK for the CPU related functions and to generate DMACLK
32KHz for the real time clock
2/10/95
Subject to change without notice
143
Preliminary
Functional Description
CS4041