F84045 Asiliant Technologies, F84045 Datasheet - Page 48

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
34
35
36
37
38
Revision 1.0
Index
dec0 Index dec1 Index
38
0
1
2
3:6
7
30
31
32
33
CPU modes CLKINmode
Function
Bits
Memory decode #1 address low.
Memory decode #1 address high.
Memory decode #1 size and destination.
Memory decode #1 attributes.
CPU Modes.
HITM# Sampling.
HITM# Sample Point
SUSPA# Enable
(Reserved)
CLKIN Mode (Latched state of NMI pin during power-on reset. Not writeable.)
2/10/95
34
35
36
37
0
1
destination
D7
add high
function
add low
attrib
Description
Default = 00. Typical setting = 00 for 1X clock mode and WT CPU cache.
L1 Write Through. DRAM and cache controllers do not wait for HITM#. The
L1 Write Back. DRAM and cache controllers wait for HITM# on all non-CPU
0
1
0
1
0
1
HITM# pin is disabled in this mode and may be used as a general purpose input
bit.
generated memory cycles.
D6
A23
A31
D7
Subject to change without notice
-
-
VL local
A22
A30
D6
D5
-
2 clocks after ADS# (end of first T2)
3 clocks after ADS# (end of second T2)
Disable SUSPA# pin
Enable SUSPA# pin (intende d for Cyrix CPUs)
NMI sampled high during reset, signifying 1X CLKIN mode
NMI sampled low during reset, signifying 2X CLKIN mode
Default = 00. See Index 33h.
A21
A29
hole
47
D5
Default = 00. See Index 30h.
-
Default = 00. See Index 31h.
D4
A20
A28
D4
Default = 00. See Index 32h.
-
-
D3
Size3
A19
A27
D3
-
gen EADS
D2
Size2
A18
A26
D2
-
hitm# sample
Configuration Registers
Preliminary
D1
cache1
Size1
A17
A25
D1
cache0
Size0
L1 wb
A16
A24
D0
D0
CS4041