F84045 Asiliant Technologies, F84045 Datasheet - Page 51

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
3F
40
41
Revision 1.0
Index
3D
3C
3E
3F
0
1
2
3
4
5
7:6
0
1
2
3
4
5
6
7
GPout data
GPin data
GP select
GP select
Function
Bits
General Purpose Input data register (read only).
This register reads the current state of the listed pins. These pins may be read regardless of the
selected function for the pins. This register is intended to be read-only. Writing to this register may
cause GPOUT signals to malfunction.
LDEV1# pin
LDEV2# pin
GPA pin
(Reserved)
MCLK pin
MDATA pin
(Reserved)
(Reserved)
IDE Enables and Control Functions.
IDE Connector 1 enable (Addresses 1F0:1F7, 3F6:3F7)
IDE Connector 2 enable (Addresses 170:177, 376:377)
IDE Connector 3 enable (Addresses 5F0:5F7, 7F6:7F7)
IDE Connector 4 enable (Addresses 570:577, 776:777)
IDE Command Start. This specifies the earliest that the IDE commands may go active for local bus
IDE Data hold. This bit specifies how long IDEEN# is held low following IDEIOW# going high, and
Force Defaults.
Use SBHE# for A2.
2/10/95
data port accesses.
how long RDY# is delayed.
0
1
0
1
0
1
0
1
0
1
gpDsel1
gpBsel1
flushsel
D7
-
Description
Disabled. Accesses go to the ISA bus. IDEEN#, IDECS0:1# not active.
Enabled. Accesses go to the 4041 IDE logic.
IDE commands may go active at the end of the first T2.
IDE commands may go active at the end of the Second T2
1 T state
2 T states.
Default value forcing is disabled.
IDECS0:1#, XA0:1, and SBHE# are forced to 0 by default.
SBHE# is always SBHE#. Address setup timer starts at T1.
SBHE# is used for IDEA2. Address setup timer starts when the addresses are forced
gpBsel0
gpDsel0
to their defaults.
D6
-
-
Subject to change without notice
FLUSH#
GPAsel1
MDATA
gpCsel1
D5
50
gpAsel0
gpCsel0
MCLK
GPD
D4
Typical setting = C3h for 2 local IDE connectors.
ldev1sel1
ras6sel1
GPC
D3
-
ldev1sel0
ras7sel0
GPB
GPA
D2
ldev0sel1
LDEV2#
ras6sel1
RAS7#
Configuration Registers
Preliminary
D1
ldev0sel0
LDEV1#
ras6sel0
RAS6#
D0
CS4041