F84045 Asiliant Technologies, F84045 Datasheet - Page 137

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Reset the 486 while changing frequencies. This method uses the STPCLK# output of the 4041 to reset the 486 while
the clock is being switched. STPCLK# is inverted and ORed with CPURESET. The CPU will be reset before
switching clock frequencies, and taken out of reset 1mS after the switch. The reset vector must be capable of figuring
out that this is the cause of the reset.
Intel S Series
The S series has a STPCLK# function and SMM. It has a PLL, and requires the use of STPCLK#, with a 1mS delay
between changing the frequency and removing STPCLK#. Either hardware or software power management may be
used. The 4041 should wait for the Stop Clock Acknowledge bus cycle.
If 2x clock mode is used the clock may be changed instantaneously without STPCLK#. It is not recommended to use
this because it will not work with DX2s or P24Ts.
AMD DX2. Same as Intel DX2. It has a PLL.
AMD S Series
These are basically the same as Intel, with PLL.
Cyrix S & S2 CPUs
The Cyrix parts have the same basic functionality as the S series. The "PLL" is static, and may have the frequency
changed at any time. Future Cyrix CPUs may contain a PLL and require using the SUSPA# signal when switching the
clock.
5.15. Internal Keyboard/Mouse Controller
The 4041 contains a state-machine implementation of a PS/2 compatible keyboard/mouse controller, eliminating the
need for an external 8042 microcontroller device. The 4041 implementation is entirely state-machine and gating-tree
based; there is no internal microcontroller, microcode, or ROM of any kind. Even the translation of keyboard scan
codes to standard PS/2 keycodes is done with a gating tree rather than a ROM. As compared to a general-purpose 8042
microcontroller, the 4041 implements the subset of 8042 features needed for a PS/2 compatible keyboard and mouse
controller. (The internal controller can be disabled, if desired, to allow an external 8042 or equivalent to be used.)
Host CPU software communicates with the keyboard/mouse controller via two I/O addresses ("host CPU" refers to the
main system CPU, 486-family):
Reading from 64h. Controller status can be read at any time from I/O address 64h. The status following system reset
is 00h. Controller status bit assignments are as follows:
Revision 1.0
64h -- status (read), or host command (write)
60h -- data read/write (8-bit)
7
6
5
4
3
2
1
0
(Not used; read as 0)
Timeout during transmission to or from keyboard or mouse
Mouse Data Available in Controller Output Buffer
Inhibit Switch (KBINH# signal), ‘1’ = high
Command/Data (1/0) last written to 64h/60h
System Flag (1 usually means a switch from Protected to Real Mode)
Controller Input Buffer Full (last write to 60h/64h still pending)
Controller Output Buffer Full (data available to read at port 60h)
2/10/95
Subject to change without notice
136
Preliminary
Functional Description
CS4041