F84045 Asiliant Technologies, F84045 Datasheet - Page 114

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.10.4. DRAM Refresh
Refresh is always hidden, regardless of who owns the bus.
needed to allow refresh to occur, but HOLD-HLDA protocol is never used for refresh. DRAM refresh is always CAS-
before-RAS (no refresh address required on the MA bus). To reduce power surges during DRAM refresh, RAS#
signals are staggered as shown in the table below.
Refresh requests are received from the 4045 through the control link. Refresh request pulses are received from the
control link decoder in the 4041, and sent to the ISA state machine and the DRAM controller. The ISA state machine
arbitrates the refresh request with the ISA bus controller for ISA refresh, sending an acknowledge back across the link
when the bus is available (assuming ISA refresh is enabled).
DRAM refresh is done separately from ISA refresh. The DRAM controller arbitrates the refresh request with internal
DRAM activity, and performs the refresh cycle when it is able. This may or may not coincide with the ISA refresh, and
is generally much shorter than the ISA refresh. Since the MA bus is not required for refresh, the DRAM refresh may
occur during an ISA bus access (which uses the MA bus as SD8:15).
5.10.5. DRAM Parity
Parity is generated by the CPU when it has control, and by the 4041 at all other times, including parity for VL bus
masters, ISA Masters, DMA, and secondary cache castout cycles. Parity is generated asynchronously from the
unlatched CPU data bus. Since the CPU generates even parity, the 84041 generates and expects even parity also.
Parity is on a byte basis. Even parity means that a data value of ‘FFh’ has ‘0’ for the parity bit.
Parity is checked by the 4041. It latches the data on the same clock edge as the CPU (or current master) and checks the
parity one clock later.
5.10.6. Alternate Master Accesses (VL or ISA Master, or DMA)
When a VL master accesses the DRAM, it is handled the same as if the CPU is accessing it except that the 4041
generates parity, and there is a separate timing mode register which is used which allows a more relaxed timing mode
to be used.
Revision 1.0
Table 5.22: Staggered Refresh Set Assignment
RASn#
RASm#
CAS#
DWE#
MEMCS#
2/10/95
Set #
1
2
0, 2, 5, 7
1, 3, 4, 6
RASes
Subject to change without notice
Figure 5.15: Refresh cycle
No RASes are active or a RAS in set 2 is active.
A RAS in set 1 is active
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The CPU or alternate master is held in wait states as
Goes first if:
RAS# precharge = 2
Preliminary
Functional Description
CS4041