F84045 Asiliant Technologies, F84045 Datasheet - Page 22

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

A24:27, A31
ROMCS# / KBCS#
LDEV0:2#
Cache Controller
CA2
CA3A, CA3B
CRDA#, CRDB#
#CWEA, CWEB#
TAGWE#
TAG0:10
DRAM Controller
RAS0:7#
CAS0:3#
DWE#
MA0:1
MA2:9/XD8:15 138, 137, 136, 132, 131, 130, 129, 128
MA10:11
Revision 1.0
165, 164, 163, 162, 161
104
85,86,87
7
8, 9
12
201, 200, 199, 198, 197, 196, 190, 189, 188, 187, 186
151, 150, 149, 148, 155, 154, 153, 152
146, 145, 143, 142
141
140, 139
135, 134
2/10/95
I/O
OUT
OUT
OUT
6, 5
11, 10 OUT
OUT
I/O
OUT
OUT
OUT
I/O
Local bus address. Driven low for DMA and ISA master cycles.
Logical OR of the R OM chip select and 8042 chip select. The 8042 chip select is
IN Local Device. A local bus slave or cache controller drives these signals low to
Cache address bit 2 for a single bank cache. Upper most data SRAM address bit
Cache address bit 3 for each bank of a double bank cache. CA3A used for a single
OUT
Tag Write enable. Driven low during L2 read miss cycles and when changing the
Tag RAM bits. TAG0 is the dirty bit. 8, 9, and 11 bit tags are supported. TAG0:7
RAS for each of 8 DRAM banks. Direct Drive.
CAS0:3 for each byte of DRAM Direct drive for up to 2 banks of DR AM.
DRAM write enable. Direct drive for 2 banks of DRAM. Also used to control the
DRAM address/upper data bus. Direct drive for up to 2 banks of DRAM. During
active for I/O ports 60 and 64. The ROM chip select is programmable.
indicate that it will handle the cycle. This signal is sampled either at the end of
the first or second T2. LDEV1# and LDEV2# may be redefined as other inputs.
They are disabled at power up. LDEV0# is enabled at power up.
(A15,16,17,18,or 19) for a double bank cache.
bank.
used for a single bank.
used for a single bank. Generated from CWS#.
dirty bit from clean to dirty.
is always used for 8 bit tag, TAG0:8 for 9 bit tag. Unused bits must be pulled
up.
direction of external DRAM data buffers if used.
ISA cycles MA2:9 become XD8:15 respectively (the upper byte of ISA bus
data). They are buffered with a 245 to generate SD8:15. MA0:1 and 10:11 are
output only.
Subject to change without notice
Cache Read strobe for each bank of a double bank cache. CRDA#
Cache Write strobe for each bank of a double bank cache. CRDA#
21
Preliminary
Pin Descriptions
CS4041