F84045 Asiliant Technologies, F84045 Datasheet - Page 45

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F84045

Manufacturer Part Number
F84045
Description
Manufacturer
Asiliant Technologies
Datasheet

Specifications of F84045

Lead Free Status / Rohs Status
Not Compliant

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Part Number:
F84045
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Quantity:
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Index
23
24
25-27
28
29
2A
Revision 1.0
Index
23
24
7:0
7:0
2:0
3
4
5
6
7
cache tag tst
cache tag tst
Function
Bits
Data port for tag testing, bits 0-7.
next). Typical setting = 00h for normal operation (value has no effect). When tag test mode is
enabled, writes to the test window cause the value in this register to be written to bits 0-7 in the TAG
RAM. Reads from the test window cause TAG bits 0-7 to be written into this register.
Data port for tag testing, bits 8-10.
next). Typical setting = 00h for normal operation (value has no effect). See index 23h description.
Register bits 0-2 are tag bits 8-10. Register bits 3-7 are reserved.
Do not exist.
I/O Decode #0 Address Low.
Index 2Bh is non-zero.
Address bits 7:0 to be compared for the decode.
I/O Decode #0 Address High.
Index 2Bh is non-zero.
Address bits 15:8 to be compared for the decode.
I/O Decode #0 Size and Mask.
Index 2Bh is non-zero.
Decode size bits. Provides the mask for bits 6:0 for address.
Mask bit for A7. 0=decode, 1=ignore the address bit.
Mask bit for A8. 0=decode, 1=ignore the address b it.
Mask bit for A9. 0=decode, 1=ignore the address bit.
Mask bit for A10. 0=decode, 1=ignore the address bit.
Mask bit for A15:11. 0=decode, 1=ignore the address bits.
2/10/95
000
001
010
011
100
101
110
111
TAG7
D7
-
Description
1 byte (port)
2 bytes (ports)
4 bytes (ports)
8 bytes (ports)
16 bytes (ports)
32 bytes (ports)
64 bytes (ports)
128 bytes (ports)
TAG6
D6
-
Subject to change without notice
TAG5
D5
-
Default = 00. Typical setting doesn't matter (no effect) unless
Default = 00. Typical setting doesn't matter (no effect) unless
Default = 00. Typical setting doesn't matter (no effect) unless
44
TAG4
D4
Default = undefined (may vary from one power up to the
-
Default = undefined (may vary from one power up to the
TAG3
D3
-
TAG10
TAG2
D2
TAG1
TAG9
Configuration Registers
Preliminary
D1
TAG0
TAG8
D0
CS4041

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