F84045 Asiliant Technologies, F84045 Datasheet - Page 117

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

There are two registers which control the timing of the ISA bus cycles. They are normally set to the default values, but
may be adjusted, especially if the ISA bus clock rate is increased. There are three adjustments:
5.11.2. DMA or ISA Master Accesses to the ISA Bus
The 4041 performs byte swapping for these cases, and controls the XD buffers to properly steer the data when the slave
is on the XD bus.
5.11.3. DMA or ISA Master Accesses to DRAM or VL Slaves
When DGNT# goes active (for DMA or ISA master cycles) the 4041 becomes an ISA bus slave, by floating the ISA
commands, and a local bus master, by driving the local bus control signals. When a DMA or ISA master cycle
attempts to access a device on the local bus, the 4041 performs the control signal translation and data steering for the
cycle. Local Slaves and DRAM are handled identically.
5.12. Fast IDE
The 4041 Fast IDE provides much higher speed access to the IDE controller data ports than the standard ISA bus
implementation, thus boosting disk performance.
Features:
The 4041 IDE controller has a direct local bus interface to speed up access to the IDE drive. Drive accesses are
speeded up by three means:
The first two will speed up any drive. The final one is very drive dependent.
Revision 1.0
Command Delays. These are adjustable separately for I/O, 8 bit memory, and 16 bit memory to be 0, 1, 2, or
3. 0 command delay activates the command on the falling edge of ALE. Each command delay added delays
the activation of the command by one-half of a BUSCLK, or 62.5nS with an 8MHz bus. Command delays cut
into the command active time. They do not extend the end of the command. That must be done by the wait
state control, or by the ISA bus slave itself by pulling IOCHRDY. The normal settings are 0 for 16 bit
memory and 1 for I/O cycles and 8 bit memory.
Wait States. This sets the standard number of wait states for bus cycles. Wait states may be added by the
slave by pulling IOCHRDY, or reduced by pulling 0WS#. The wait states are set separately for 8 bit and 16
bit slaves. 8 bit slave cycles are settable to 2, 3, 4, or 5 while 16 bit slave cycles are settable to 0, 1, 2, or 3.
Zero wait states would be a two clock TS-TC cycle. With 0 command delays, that would be a 1 clock
command. Each wait state adds a full BUSCLK. The normal values are 4 wait states for 8 bit slaves and 1
wait state for 16 bit slaves.
Address Hold Time. This setting allows RDY# to the processor to be delayed by 1 extra CPU clock after the
ISA bus command goes inactive. It will provide 1 T state of additional address hold time, as well as a longer
period between ISA bus commands. It is normally disabled.
Fast accesses to IDE drive data port
32 bit I/O cycles supported
Up to 8 drives supported (up to 4 IDE addresses)
Programmable I/O read length, I/O write length, command inactive, and address setup time
Each drive may select either of 2 programmed timing sets
May coexist with other IDE controllers at different addresses, either local bus or ISA
When enabled, it may disable an existing controller on the ISA bus
Transparently supports the 3F7 register sharing with the floppy, wherever the floppy is located
Eliminating the overhead of an ISA bus access
Allowing 32 bit I/O cycles to reduce CPU overhead (converted to two 16 bit IDE cycles)
Shortening the command timing to the drive
2/10/95
Subject to change without notice
116
Preliminary
Functional Description
CS4041