F84045 Asiliant Technologies, F84045 Datasheet - Page 119

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Externally this pin is usually connected to SD7. It may also be connected directly to the floppy's disk change pin.
5.12.1.4. IOCS16# and IOCHRDY Sampling
IOCS16# is not sampled by the fast IDE state machine. It is always assumed active for the IDE data port. If an 8 bit
drive is used (assuming any exist in the first place), that drive number should be set to generate ISA cycles for the data
port. Drives 0, 1, 2, or 3 may be set this way. Drives 4, 5, 6, and 7 may not.
Since all of the chip selects are tied together for the 4 IDE connectors, all 4 will be generating IOCS16# at the same
time. To select the proper one, an external mux is used. This is not necessary if only 1 IDE connector is implemented.
If it is desired that only 16 bit drives be supported it is not necessary even for multiple IDE connectors. IOCS16# need
not even be hooked up in this case.
IOCHRDY is sampled by the fast IDE state machine. It is sampled 1 SCLK before the command is to go inactive. If it
is low, the command will remain low until 1 SCLK after it is sampled high. The 1 clock delay is necessary for double
clocking to prevent a metastable condition.
5.12.2. Cycle Description
5.12.2.1. Data Port
The data port accesses are the ones which are sped up and optimized for. A special state machine is used for these
accesses which runs off of the CPU local bus.
The default signal states are set in anticipation of these accesses. This assures adequate address setup time to the
command strobes. These default signal states are in effect when BOTH of the following are true:
The command for the data port may be generated as early as the end of the first T2, and most of the time this is the
case. Several Timing Parameters are programmable. These are:
Revision 1.0
Table 5.25: Programmable Timing Parameters
Write Command Length
Read Command Length
Earliest Command Start
Command Recovery
Address Setup Time
Timing Parameter
Write Data Hold
ATEN is inactive (ATEN indicates an active ISA bus cycle)
DGNT# is high (indicating the CPU or VL master has the bus)
2/10/95
Table 5.24: Default signal states
# of choices
XA0, XA1, SBHE# (IDEA2)
Subject to change without notice
16
16
16
4
2
2
IDECS0#
IDECS1#
Signal
End of first or second T2
1,2,3,4,5,6,7,8,10,12,14,
16,18,20,22,24 clocks
1,2,3.....15,16 clocks
1,2,3.....15,16 clocks
1,2,3 or 4 clocks
1 or 2 clocks
118
Selections
Default
0
0
1
Separate A and B programming
Separate A and B programming
Separate A and B programming
Separate A and B programming
Per Drive Programming
One global choice.
One global choice
Preliminary
Functional Description
CS4041