F84045 Asiliant Technologies, F84045 Datasheet - Page 161

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Optionally, in the 4045, the SA19 pin may be converted to a chip enable input which may be used to decode upper
address bits, allowing a 16 bit IO decode. The chip select function is controllable from an index register. The 4041
may optionally provide a chip select signal for the SIPC to use, which is low when A10:15 are all low.
6.12. 486 Floating point logic
The SIPC has two modes for floating point error handling. It may either do the error handling support internally or
externally.
Internal mode is used for the 486, or other CPU which contains the coprocessor internally and has the FERR# and
IGNNE# signals. In this mode the SIPC receives the FERR# signal and generates IGNNE#. Internally, it generates
IRQ13 to the IPC megacell. There is no IRQ13 input signal in this mode. The internal IRQ13 and externally driven
IGNNE# signals operate as follows:
The coprocessor normally will freeze upon attempting execution of any non-control instruction that causes an error
(FERR#). Asserting IGNNE# to the coprocessor allows the error handler to execute further non-control instructions as
needed for PC/AT compatible recovery from the error condition. (Control instructions generally can be executed
anytime, with or without IGNNE#.)
Output to F1h is treated the same as output to F0h. INTCLR# is generated in response to either port being written to.
In 286/287-based systems, output to F1h caused a coprocessor reset. This is not required in 386 and 486-class systems,
but some software may still expect an output to F1h to clear a coprocessor interrupt..
External mode is used with an external coprocessor such as a Weitek coprocessor. External mode is required for the
Weitek because it generates IRQ13 directly. The FERR# pin becomes the IRQ13 input pin in this mode, and the
IGNNE# pin becomes INTCLR#, which is a decode of IO ports F0h and F1h. An external PAL uses these signals, as
well as the coprocessor error signals, to handle the AT compatible coprocessor function.
6.13. Keyboard and Mouse Interrupts.
The 4045 and 4035 both have the ability to receive IRQ1 and the mouse interrupt (usually IRQ12) directly from an
external keyboard/mouse controller. In addition, the 4045 also has the ability to receive these interrupts via the control
link from the internal keyboard/mouse controller in the 4041. When the internal controller is used, the 4041 and 4045
work together to latch IRQ1 and IRQ12 until an I/O read from port 60h occurs. The I/O read from port 60h clears the
interrupt. This is a feature of PS/2 keyboard/mouse compatibility. To clear IRQ1, port 60h is a 16-bit decode in the
4041. To clear IRQ12, port 60h is a 10-bit decode in the 4045 (optionally a 16-bit decode if the IOCS# feature is
implemented).
In systems that use an external mouse controller, IRQ12 appears on the ISA bus and potentially can be used or
monitored by other system resources. External mouse controllers sometimes drive IRQ12 with an open-collector
buffer. The 4045 implements a similar capability. When the internal mouse controller is being used, the IRQ12 pin is
driven by the 4045 as an output, as well as feeding back into the interrupt controller logic in the 4045. The pin is
driven high when the mouse interrupt is asserted, and driven low whenever the mouse interrupt is de-asserted. The
4045 floats IRQ12 when the internal mouse option is disabled. IRQ1, unlike IRQ12, is not driven out when the
internal keyboard controller is used.
Revision 1.0
The falling edge of FERR# causes internal IRQ13 to become asserted, interrupting the CPU. Meanwhile, the
When the IRQ13 interrupt handler issues an output to F0h, an internal INTCLR# is generated. This clears IRQ13
IGNNE# remains driven low until the IRQ13 interrupt handler issues a coprocessor command that results in FERR#
coprocessor freezes on the error-causing coprocessor instruction.
and causes IGNNE# to become driven low, unfreezing the coprocessor so that the interrupt handler can execute
further coprocessor instructions as needed for error recovery. FERR# is still low at this point.
returning to the high state.
2/10/95
Subject to change without notice
160
Preliminary
Functional Description
CS4041