F84045 Asiliant Technologies, F84045 Datasheet - Page 70

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

This section describes each CHIPSet function from a system standpoint. Each subsection lists the basic features, board
level implementation and options, and which chip(s) the function is contained in. The detailed operation is described in
the individual chip specs, which follow this section. Extensive cross-references to the other sections have been
provided to aid in locating all applicable information on a given topic.
4.1. Clocks
Either a 1x or 2x clock is provided to the 4041 CLKIN pin from an oscillator. The 2x clock is needed only for the
highest speed DRAM mode (3-2-2-2 burst read), which is used at lower clock frequencies. The oscillator goes through
the clock dividing and switching logic, which allows the power management system to slow down the system clock.
This goes to three clock outputs, all produced at low skew with respect to each other:
These clocks are normally buffered with a 74F244, and distributed to the system, including being fed back into the
4041 for use by the rest of the internal logic.
Clock switching optionally may be done with a clock generator chip. Some clock generator chips switch frequencies
slowly enough for the CPU VCO to remain locked. This allows power management with a standard 486 CPU.
For further information, see Sections 5.2 and 6.2.
4.2. Reset and GATEA20
The reset and GATEA20 logic is contained in the 4045.
The 4045 receives the reset (PWRGOOD) from the power supply or power up clear logic. It also receives CPU restart
commands from the following sources: the 8042 (or emulation of the 8042) across the control link from the 4041; port
92, which is internal to the 4045; and config register reset. The 4045 generates SYSRESET and CPURESET.
SYSRESET goes active only in response to PWRGOOD (due to power up or pushing a RESET button). CPURESET
goes active for CPU soft restarts also.
CPU restarts may be redirected to generate an SMI rather than reset the CPU to avoid SMI and SRESET collision
problems.
A20 is gated in the CPU only. The 4045 provides A20M#, which is the OR of the port 92 GATEA20 and the
GATEA20 from the 4041, which is sent across the link. This consists of the 8042 GATEA20 (internal, emulated, or
external) and the SMM GATEA20.
For further information, see Sections 5.3, 6.3, and 6.4. The Control Link is described in Section 4.3.1.
Revision 1.0
CLK2OUT
SCLKOUT
CPUCLK
2/10/95
4. System Level Functions and Cross References
Table 4.1: CPU Chip Reset Signal Routing
CPU with SRESET input
2x clock, fed back into the 4041. Does not stop. This clock is 1x if a 1x clock is provided on
CLKIN.
1x clock for everything except the CPU. Does not stop.
1x clock to the CPU. May be stopped in stop-clock mode
Standard 486
CPU Type
Subject to change without notice
SYSRESET signal
RESET pin
69
-
CPURESETsignal
SRESET pin
RESET pin
System Level Functions
Preliminary
CS4041