F84045 Asiliant Technologies, F84045 Datasheet - Page 64

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

3.5. 84045 Configuration Registers
Index
01
Revision 1.0
7:6
5:4
3:2
1
0
Bits
DMA WAIT STATE CONTROL.
See Index 0Ah for programming of 4045 internal BUSCLK frequency.
IPC I/O wait states. Controls the number of wait states (4045 internal BUSCLK cycles) added to any
16-bit DMA wait states. These bits control the num ber of wait states (DMACLK cycles) inserted
8-bit DMA wait states. These bits control the number of wait states (DMACLK cycles) inserted
DMA MEMR# signal extension. In the IBM PC/AT, the assertion of MEMR# is delayed by one
DMACLK clock select.
2/10/95
I/O access to an IPC I/O port (00-0Fh, 20-21h, 22-23h, 40-43h, 71h, 80-8Fh, A0-A1h, C0-DFh).
Port 70h is decoded outside the IPC megacell does not have any added wait states. The 4045
pulls IOCHRDY as needed to insert the wait states.
during 16-bit DMA transfers.
during 8-bit DMA transfers.
DMA wait states are defined as DMACLK cycles (see Index 0Ah) added to the IOW# or
MEMW# command low time. Minimum command low time (one wait state) is two DMACLK
cycles total. The 4041 may pull IOCHRDY as needed to add additional DMA wait states for
local bus timing.
DMACLK cycle compared to IOR#. This may not be desirable in some systems.
PC/AT)
Description
00
01
10
11
00
01
10
11
00
01
10
11
0
1
0
1
Subject to change without notice
One wait state
Two wait states
Three wait states
Four wait states
One wait state (default)
Two wait states
Three wait states
Four wait states
One wait state (default)
Two wait states
Three wait states
Four wait states
Delay MEMR# by one DMACLK (default, PC/AT compatible)
MEMR# not delayed; follows same timing as IOR#
DMACLK cycle is two 4045 BUSCLK cycles (default, as in
DMACLK cycle is one 4045 BUSCLK cycle
63
Default = C0h. Typical setting = 00h.
Configuration Registers
Preliminary
CS4041