F84045 Asiliant Technologies, F84045 Datasheet - Page 129

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Programmable options:
5.14.1.2. Power Management for SMI CPUs
For SMI capable CPUs, greater control of power management is possible. This includes multiple levels of power
control, better control of stopping the CPU clock, and the ability to shut down other devices, including video, under
software control.
The activity timer causes an SMI when the system is idle. The SMM code then chooses the appropriate clock
frequency to switch to. It may also put other devices in a low power mode, if desired. It may then setup the activity
timer to trigger at a different interval, or a different set of events to reset it to go into a further low power mode.
A wake up event also causes an SMI. The SMM code then picks the level of system performance according to the
event which caused the wake up.
If the SMM code stops the CPU clock (with the STPCLK function) a wake up event, including an INTR will restart the
clock and issue the SMI.
5.14.2. SMI Sources
The SMI sources are as follows:
Two index registers indicate which sources have requested an SMI. The MSB of register A indicates whether any bits
in register B are set. Multiple bits may be set if several sources happen at once. Bits may continue to be set while in
SMM. Writing a 1 to the register at any bit position (other than the MSB of register A) will clear that bit.
Two more index registers enable the sources of SMI interrupts. The bit encoding is the same as that of the SMI status
registers except that the MSB of register A is a global enable for SMI. If SMI# is still low upon exiting from SMM, the
global enable should be toggled before exiting SMM to guarantee that the SMI# pin toggles. This need not be done if
index 90h reads as 00, since this indicates that the SMI# pin is inactive (high).
Revision 1.0
TimerA:
Timer B:
Stop clock options
TimerA time-out
TimerB time-out
Wake up EventA
Wake up EventB
I/O Restart
Halt bus cycle
CPU restart request.
External SMI source (either of two pins)
Software SMI
2/10/95
Interval
What resets it
Interval
What resets it
Do not stop clock
Pull STPCLK pin
Stop the actual CPU clock
Pull STPCLK pin and stop the CPU clock.
Subject to change without notice
128
Preliminary
Functional Description
CS4041