F84045 Asiliant Technologies, F84045 Datasheet - Page 140

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

(C0h) Read Input Port. The contents of the Input Port are placed in the Controller Output Buffer for reading by the
host CPU. The Input Port is a subset of the P10-P17 Input Port found in an 8042. Bit assignments:
(D0h) Read Output Port. The contents of the Output Port are placed in the Controller's Output Buffer for reading by
the host CPU. The Output Port is a subset of the P20-P27 Output Port found in an 8042. Bit assignments:
(D1h) Write Output Port. The next data byte written to port 60h is placed in the Output Port. See D0h command
above for bit assignments.
(D4h) Transmit to Mouse. The next data byte written to port 60h is transmitted to the mouse. The execution time of
this command depends on mouse timing.
(E0) Read Test Inputs. The Test Inputs are internal equivalents of the T0 and T1 input pins found on an 8042. Bit
assignments are as follows:
(F0-FFh) Pulse Output Port. A '0' in bits 0-3 causes the corresponding Output Port bit to be pulsed low for 6
minimum. Pulsing bits 2 or 3 has no effect, since these Output Port bits aren't used. The most typical use of this
feature is to pulse the CPU reset request line. An FFh command executes immediately (same ISA cycle as host
command).
5.15.1.1. Serial Data and Clock
Data transmissions to and from the keyboard and mouse utilize an 11-bit serial transmission format consisting of a start
bit, 8 data bits (LSB sent first), parity bit, and stop bit. Parity is odd, meaning that a data value of FFh has a 1 for the
parity bit. A bit value of 1 corresponds to a high logic level, and 0 corresponds to low. The start bit is always a 0, and
the stop bit is always a 1. The clock and data lines remain high between transmissions except as described below for
higher level communication protocol.
Revision 1.0
If additional general-purpose I/O signals are needed, they can be implemented using GPIO pins on the 4041.
See Index Registers 3C-3Fh (multifunction pins).
7
6:2
1
0
7:6
5
4
3:2
1
0
7:2
1
0
2/10/95
Keyboard Inhibit input (LDEV2# pin; see Index 3Ch)
(Not used; read as 0)
Mouse data input
Keyboard data input
(Not used; read as 0)
Mouse interrupt, IRQ12 (latched in the 4045)
Keyboard interrupt, IRQ1 (latched in the 4045)
(Not used; always 0)
Gate A20 function, affects A20M- via the 4045
CPU Reset request, causes CPU reset (via the 4045) or SMI
(Not used, read as 0)
Mouse clock input
Keyboard clock input
Subject to change without notice
139
Preliminary
Functional Description
CS4041
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