TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 104

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

RXD pin
Shift register
UARTSR<PERR>
INTRXD
RXD pin
Shift register
UARTSR<FERR>
INTRXD
2.11.9 Status Flag/Interrupt Signal
(1) Parity error
(2) Framing error
bit, the parity error flag UARTSR<PERR> is set to “1”. The UARTSR<PERR> is
cleared to “0” when the RDBUF is read after reading the UARTSR.
UARTSR<FERR> is set to “1”. The UARTSR<FERR> is cleared to “0” when the
RDBUF is read after reading the UARTSR.
When parity determined using the receive data bits differs from the received parity
When “0” is sampled as the stop bit in the receive data, framing error flag
xxxx0**
xxx0**
Figure 2.11.6 Generation of Framing Error
Figure 2.11.5 Generation of Parity Error
Final bit
Parity
86FM48-100
pxxxx0*
xxxx0*
Stop
Stop
1pxxxx0
1xxxx0
Reading UARTSR then
RDBUF clears FERR.
Reading UARTSR then
RDBUF clears PERR.
TMP86FM48
2007-08-24