TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 53

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

P1OUTCR
Read only
(1FEEH)
(0001
(000B
P1PRD
P1DR
2.2.2
R/W
H
H
)
)
P1OUTCR
Port P1 (P17 to P10)
serial interface input/output and timer/counter input/output. It can be selected whether
output circuit of P1 port is CMOS output or a sink open drain individually, by setting the
output circuit control (P1OUTCR). When a corresponding bit of P1OUTCR is cleared to “0”,
the output circuit is selected to a sink open drain and when a corresponding bit of
P1OUTCR is set to “1”, the output circuit is selected to a CMOS output.
serial interface input, timer/counter input), the respective output latch (P1DR) should be
set to “1” and its corresponding P1OUTCR bit should be cleared to “0”.
output), the respective P1DR should be set to “1”.
respective address. When read the output latch data, the P1DR should be read and when
read the terminal input data, the P1PRD register should be read.
P17
P17
7
Port P1 is a 8-bit input/output port which is also used as an external interrupt input,
When used as an input port or a secondary function input (External interrupt input,
When used as a secondary function output (Serial interface output or timer/counter
During reset, the P1DR is initialized to “1” and P1OUTCR is initialized to “0”.
P1 port output latch (P1DR) and P1 port terminal input (P1PRD) are located on their
Data input (P1PRD)
Data output (P1DR)
Data input (P1DR)
P1OUTCRi input
Control output
P16
P16
Port P1 output circuit control
(Set for each bit individually)
Control input
6
P1OUTCRi
OUTEN
STOP
P15
TC1
P15
5
INT3
P14
TC3
P14
4
Figure 2.2.3 Port 1
PWM5
D
PDO5
Output latch
P13
TC5
P13
D
3
86FM48-49
0: Sink open-drain output
1: CMOS output
Q
Q
SCK2
P12
P12
2
P11
P11
SI2
1
SO2
P10
P10
0
(Initial value: 1111 1111)
(Initial value: 0000 0000)
Note: i = 7 to 0
P1i
TMP86FM48
2007-08-24
R/W