TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 117

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

PIN
INTSBI
interrupt
request
SCL pin
SDA pin
2.12.6 Data Transfer of I
(1) Device initialization
(2) Start condition and slave address generation
Specify the data length to 8 bits to count clocks for an acknowledge signal. Set a
transfer frequency to the SCK in SBICRA.
addressing format.
default setting to a slave receiver mode, clear “0” to the MST, TRX and BB in SBICRB,
set “1” to the PIN, “10” to the SBIM, and “00” to bits SWRST1 and SWRST0.
the SBIDBR.
bus and then, the slave address and the direction bit which are set to the SBIDBR are
output. An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle,
and the PIN is cleared to “0”. The SCL pin is pulled-down to the low level while the PIN
is “0”. When an interrupt request occurs, the TRX changes by the hardware according
to the direction bit only when an acknowledge signal is returned from the slave device.
Figure 2.12.11 Start Condition Generation and Slave Address Transfer
Note: The initialization of a serial bus interface circuit must be complete within the time
Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If
Note 2: The bus free must be confirmed by software within 98.0 µs (The shortest
Start condition
For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”.
Next, set the slave address to the SA in I2CAR and clear the ALS to “0” to set an
After confirming that the serial bus interface pin is high level, for specifying the
Confirm a bus free status (BB = 0).
Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to
By writing “1” to the MST, TRX, BB and PIN, the start condition is generated on a
from all devices which are connected to a bus have initialized to and device does
not generate a start condition. If not, the data can not be received correctly because
the other device starts transferring before an end of the initialization of a serial bus
interface circuit.
data is written to the SBIDBR, data to been outputting may be destroyed.
transmitting time according to the I
address to be output. Only when the bus free is confirmed, set “1” to the MST, TRX,
BB, and PIN to generate the start conditions. If the writing of slave address and
setting of MST, TRX, BB and PIN doesn’t finish within 98.0 µs, the other masters
may start the transferring and the slave address data written in SBIDBR may be
broken.
A6
1
2
C Bus
A5
2
A4
Slave address + Direction bit
3
86FM48-113
A3
4
A2
5
2
C bus standard) after setting of the slave
A1
6
A0
7
R/
W
8
9
Acknowledge
signal from a
slave device
TMP86FM48
2007-08-24