TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 70

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.6
(0036
TBTCR
H
Data output
Divider Output (DVO)
for piezoelectric buzzer drive. Divider output is from pin P51 (
should be set to “1”.
Note: Selection of divider output frequency must be made while divider output is disabled.
)
fc/2
fc/2
fc/2
fc/2
Approximately 50% duty pulse can be output using the divider output circuit, which is useful
Table 2.6.1 Divider Output Frequency (Example: at fc = 16.0 MHz, fs = 32.768 kHz)
Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
13
12
11
10
DVOEN
DVOEN
DVOCK
or fs/2
or fs/2
or fs/2
or fs/2
7
Also, in other words, when changing the state of the divider output frequency from enabled to
disable, do not change the setting of the divider output frequency.
Divider output control register
DVOCK
5
4
3
2
Output latch
6
Divider output enable/disable
Divider output (
frequency selection [Hz]
D
Example: 1.95 kHz pulse output (at fc = 16.0 MHz)
DVOCK
DVOCK
(a) Configuration
2
MPX
A
B
C
D
S
00
01
10
11
Y
Q
TBTCR
5
Figure 2.6.1 Divider Output Control Register
(DV7CK) (TBTEN)
NORMAL1/2, IDLE1/2 Mode
DVO
DV7CK = 0
SET
LD
LD
DVOEN
15.625 k
4
1.953 k
3.906 k
7.813 k
)
Figure 2.6.2 Divider Output
Divider Output Frequency [Hz]
3
(P5DR).1
(TBTCR), 00000000B
(TBTCR), 10000000B
86FM48-66
0: Disable
1: Enable
00
01
10
11
P51 (
DV7CK = 1
2
DVO
1.024 k
2.048 k
4.096 k
8.192 k
DV7CK = 0
P51 output latch
DVOEN
DVO
)
(TBTCK)
fc/2
fc/2
fc/2
fc/2
pin output
NORMAL1/2 Mode
13
12
11
10
1
SLOW, SLEEP
0
;
;
;
1.024 k
2.048 k
4.096 k
8.192 k
DV7CK = 1
Mode
(b) Timing Chart
P51 output latch ← “1”
DVOCK ← “00”
DVOEN ← “1”
(Initial value: 0000 0000)
fs/2
fs/2
fs/2
fs/2
DVO
5
4
3
2
). The P51 output latch
MPX: Multiplexer
SLOW, SLEEP
Mode
fs/2
fs/2
fs/2
fs/2
TMP86FM48
5
4
3
2
2007-08-24
R/W