TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 111

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Mode
Master
Slave
(1) Acknowledgement mode specification
(2) Number of transfer bits
(3) Serial clock
SDA
transmitting and receiving data.
transmissions are always executed in 8 bits. Other than these, the BC retains a
specified value.
a.
b.
a.
Table 2.12.1 SCL and SDA Pins Status in Acknowledgement Mode
The BC (Bits7 to 5 in SBICRA) is used to select a number of bits for next
Since the BC is cleared to “000” as a start condition, a slave address and direction bit
should be set to “1”. When a serial bus interface circuit is a master mode, an
additional clock pulse is generated for an acknowledge signal. In a slave mode, a
clock is counted for the acknowledge signal.
acknowledge signal from the receiver during additional clock pulse cycle. In the
master receiver mode, the SDA pin is set to low level generation an acknowledge
signal during additional clock pulse cycle.
which is set to the I2CAR or when a “GENERAL CALL” is received, the SDA pin is
set to low level generating an acknowledge signal. After the matching of slave
address or the detection of “GENERAL CALL”, in the transmitter, the SDA pin is
released in order to receive an acknowledge signal from the receiver during
additional clock pulse cycle. In a receiver, the SDA pin is set to low level
generation an acknowledge signal during additional clock pulse cycle after the
matching of slave address or the detection of “GENERAL CALL”
“0”.
output from the SCL pin in the master mode. Set a communication baud rate that
meets the I
the equations shown below.
Acknowledgment mode (ACK = “1”)
Non-acknowledgment mode (ACK = “0”)
Clock source
When slave address matches
or a general call is detected
After matching of slave
address or general call
To set the device as an acknowledgment mode, the ACK (Bit4 in SBICRA)
In the master transmitter mode, the SDA pin is released in order to receive an
In a slave mode, when a received slave address matches to a slave address
The Table 2.12.1 shows the SCL and SDA pins status in acknowledgment mode.
To set the device as a non-acknowledgement mode, the ACK should be cleared to
In the master mode, a clock pulse for an acknowledge signal is not generated.
In the slave mode, a clock for a acknowledge signal is not counted.
The SCK (Bits2 to 0 in SBICRA) is used to select a maximum transfer frequency
SDA
SCL
SCL
Pin
2
C bus specification, such as the shortest pulse width of t
86FM48-107
Released in order to receive an
acknowledge signal.
Released in order to receive an
acknowledge signal.
Transmitter
A clock is counted for the acknowledge signal.
−
An additional clock pulse is generated.
Set to low level generating an
acknowledge signal
Set to low level generating an
acknowledge signal.
Set to low level generating an
acknowledge signal.
Receiver
TMP86FM48
LOW
2007-08-24
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