TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 96

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Internal clock
Up counter
TC5DR
Timer F/F5
INTTC5
interrupt
PDO5
pin output
(3) Programmable divider output (PDO) mode
duty cycle of about 50%. The counter counts up on an internal source clock. If the timer
value matches TC5DR, the timer F/F5 is inverted, and the counter is cleared,
generating an INTTC5 interrupt. The counter keeps counting up, and the timer F/F5 is
inverted each time the timer value matches TC5DR. The P13 (
inversion of the timer F/F5 output level.
timer when the PDO output is low may cause the duty cycle to become smaller than the
set value.
“1”.
The programmable divider output (PDO) mode is intended to output a pulse having a
At a reset or when the timer stops, the timer F/F5 is cleared to “0”. So, stopping the
To use the programmable divider output mode, set the output latch of the P13 port to
0
Example: Output a 1024 Hz pulse (at fc = 16 MHz)
n
1
Match detect
2
Figure 2.10.3 PDO Mode Timing Chart
LD
SET
LD
LD
n
0
1
(TC5CR), 00000110B
(P1DR). 3
(TC5DR), 3DH
(TC5CR), 00100110B
86FM48-92
2
n
0
1
2
;
;
;
;
Sets PDO mode
(TC5M = 10, TC5CK = 001)
P13 output latch ← 1
1/1024 ÷ 2
Starts TC5
n 0
1
7
/fc ÷ 2 = 3DH
2
PDO5
) pin outputs an
n 0
TMP86FM48
2007-08-24
1