TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 133

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

b.
1. Starting the receive operation
2. During the receive operation
3. Stopping the receive operation
Receive mode
The receive mode is selected by writing “01” to SIO1CR<SIOM>.
Receive mode is selected by setting “01” to SIO1CR<SIOM>. Serial clock is
selected by using SIO1CR<SCK>. Transfer direction is selected by using
SIO1CR<SIODIR>.
After SIO1CR<SIOS> is set to “1”, SIO1SR<SIOF> is set synchronously to “1”
the falling edge of
Synchronizing with the
sequentially from SI1 pin with the direction of the bit specified by
SBIDIR<SIODIR>.
SIO1SR<SEF> is kept in high level, between the first clock falling edge of
When 8-bit data is received, the data is transferred to SIO1RDB from shift
register. INTSIO1 interrupt request is generated and SIO1SR<RXF> is set to
“1”.
Note: In internal clock operation, when the SIO1CR<SIOS> is set to “1”, the
The SIO1SR<RXF> is cleared to “0” by reading a data from SIO1RDB.
In the internal clock operation, the serial clock stops to “H” level by an
automatic-wait function when the all of the 8-bit data has been received.
Automatic-wait function is released by reading a received data from SIO1RDB.
Then, receive operation is restarted after maximum 1-cycle of serial clock.
In external clock operation, after SIO1SR<RXF> is set to “1”, the received
data must be read from SIO1RDB before the next data shift-in operation is
finished.
If received data is not read out from SIO1RDB, receive error occurs
immediately after shift operation is finished. Then INTSIO interrupt request
is generated after SIO1SR<RXERR> is set to “1”.
There are two ways for stopping the receive operation.
SCK1
•
•
The way of clearing SIO1CR<SIOS>.
When SIO1CR<SIOS> is cleared to “0”, receive operation is stopped after
all of the data is finished to receive. When receive operation is finished,
SIO1SR<SIOF> is cleared to “0”.
In external clock operation, SIO1CR<SIOS> must be cleared to “0”
before SIO1SR<SEF> is set to “1” by starting the next shift operation.
The way of setting SIO1CR<SIOINH>.
Receive operation is stopped immediately after SIO1CR<SIOINH> is set
to “1”. In this case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB register
and SIO1TDB register are initialized.
pin and eighth clock falling edge.
serial clock is generated from
clock frequency.
86FM48-129
SCK1
pin.
SCK1
pin’s rising edge, the data is received
SCK1
pin after maximum 1-cycle of serial
TMP86FM48
2007-08-24