TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 90

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(2) Event counter mode
counts up on the rising edge of the TC3 pin input and when its value matches the
TC3DRA set value, it is cleared while at the same time generating an INTTC3
interrupt.
TC3 pin keeps high level after the rising, the detection of match is not executed and
INTTC3 is not generated until the level of TC3 pin becomes low.
machine cycles are required for both the “H” and “L” levels of the pulse width.
TC3CR<ACAP> to “1” (Auto-capture function).
(RD instruction) of TC3DRB. Loading the contents of up counter is not synchronized
with counting up. The contents of over flow (FFH) and 00H can not be loaded correctly.
It is necessary to consider the count cycle.
“H” width
“L” width
In this mode, events are counted on the edge of the TC3 pin input. The counter
The detection of match is executed at the falling edge of the TC3 pin. Therefore, if the
The minimum input pulse width of the TC3 pin is shown in Table 2.9.2. One or more
The current contents of up counter are loaded into TC3DRB by setting
The contents of up counter can be easily confirmed by executing the read instruction
Table 2.9.2 Source Clock (External clock) for Timer/Counter
NORMAL1/2, IDLE1/2 Mode
2
2
2
2
/fc
/fc
Minimum Input Pulse Width [s]
86FM48-86
SLOW1/2, SLEEP1/2 Mode
2
2
2
2
/fs
/fs
TMP86FM48
2007-08-24