TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 164

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

EEPCR<MNPWDW>
EEPSR<EWUPEN>
EEPSR<BFBUSY>
FLASH warm-up counter
FLASH control circuit status
Program execution area
Figure 2.17.6 Software-based Power Control for the FLASH Control Circuit (EEPCR<MNPWDW>)
Note 1: If the EEPSR<EWUPEN> is “0”, do not access (Fetch, read, or write) the FLASH
Note 2: To clear the EEPCR<MNPWDW> to “0”, clear the interrupt master enable flag
Note 3: If the EEPCR<MNPWDW> is “0”, generating a nonmaskable interrupt
Note 4: The EEPCR<MNPWDW> can be rewritten only when a program is being executed
Note 5: If a watchdog timer is used as interrupt request, clear the binary counter for the
Note 6: During the warm-up period with a software polling of EEPSR<EWUPEN>, if a
power for the FLASH control circuit. When the STOP mode is released, a STOP mode
oscillation warm-up is carried out, and then the CPU wait period (Warm-up for
stabilizing of FLASH power supply circuit) is automatically performed. If the
EEPCR<MNPWDW> is “0”, entering/exiting the STOP mode keeps the power for the
FLASH control circuit turned off.
If the EEPCR<MNPWDW> is “1”, entering a STOP mode forcibly turns off the
Specify MNPWDW = 0
area. Executing a read instruction or fetch to the FLASH area causes FFH to be
read. Fetching FFH results in a software interrupt occurring.
(IMF) to “0” in advance to disable an interrupt. After that, do not set IMF to “1”
during EEPSR<EWUPEN> = “0”.
automatically rewrites the MNPWDW to “1” to warm up the FLASH control circuit
(CPU wait). That time, the peripheral circuits continue operating, but the CPU stays
at a halt until the warm-up is finished.
in the RAM area. In the FLASH area, executing a write instruction to the
EEPCR<MNPWDW> does not affect its setting.
watchdog timer just before MNPWDW is changed from “1” to “0”.
nonmaskable interrupt occurs, the CPU stays at a halt until the warm-up is finished.
FLASH area
Normal operation
0
86FM48-160
Power-off state
RAM area
Specify MNPWDW = 1
Warm-up in progress
(CPU is operating)
2
10
/fc or 2
Overflow
3
/fs [s]
Software polling
Normal operation
FLASH area
TMP86FM48
0
2007-08-24