TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 45

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

1.5.2
1.5.3
1.5.4
1.5.5
Software Interrupt (INTSW)
interrupt processing (INTSW is highest prioritized interrupt).
(1) Address error detection
(2) Debugging
Undefined Instruction Interrupt (INTUNDEF)
INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to
execute it. INTUNDEF is accepted even if non-maskable interrupt is in process.
Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address,
Address Trap Interrupt (INTATRAP)
causes reset-output or address trap interrupt (INTATRAP). INTATRAP is accepted even if
non-maskable interrupt is in process. Contemporary process is broken and INTATRAP
interrupt process starts, soon after it is requested.
Note: The operating mode under address trapped, whether to be reset-output or interrupt
External Interrupts
digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as
noise).
either an external interrupt input pin or an input/output port, and is configured as an input
port during reset.
the external interrupt control register (EINTCR).
Executing the [SWI] instruction generates a software interrupt and immediately starts
Use the [SWI] instruction only for detection of the address error or for debugging.
Taking code which is not defined as authorized instruction for instruction causes
Fetching instruction from unauthorized area for instructions (Address trapped area)
The TMP86FM48 has five external interrupt inputs. These inputs are equipped with
Edge selection is also possible with INT1 to INT3.
Edge selection, noise reject control and
from a non-existent memory address during single chip mode. Code FF
instruction, so a software interrupt is generated and an address error is detected. The
address error detection range can be further expanded by writing FF
of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM or SFR areas.
break point setting address.
FF
Debugging efficiency can be increased by placing the SWI instruction at the software
as software interrupt (SWI) does.
processing, is selected on watchdog timer control register (WDTCR).
H
is read if for some cause such as noise the CPU attempts to fetch an instruction
86FM48-41
INT0
/P00 pin function selection are performed by
INT0
/P00 pin can be configured as
H
to unused areas
TMP86FM48
H
2007-08-24
is the SWI