TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 78

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(5) Pulse width measurement mode
by TC1CR<TC1S>). The trigger can be selected either the rising or falling edge of the
TC1 pin input. The source clock is used an internal clock. On the next falling (Rising)
edge, the counter contents are transferred to TC1DRB and an INTTC1 interrupt is
generated. The counter is cleared when the single edge capture mode (TC1CR<MCAP>
= “1”) is set. When double edge capture (TC1CR<MCAP> = “0”) is set, the counter
continues and, at the next rising (Falling) edge, the counter contents are again
transferred to TC1DRB. If a falling (Rising) edge capture value is required, it is
necessary to read out TC1DRB contents until a rising (Falling) edge is detected.
Falling or rising edge is selected with the external trigger TC1CR<TC1S>, and single
edge or double edge is selected with TC1CR<MCAP1>.
Note 1: Be sure to read the captured value from TC1DRB before the next trigger edge is
Note 2: If either the falling or rising edge is used in capturing values, the counter stops at “1”
Note 3: The first captured value after the timer starts may be read incorrectively, therefore,
In this mode, counting is started by the external trigger (Set to external trigger start
TC1 pin
INTTC1SW
Example: Duty measurement (resolution fc/2
PINTTC1:
SINTTC1:
VINTTC1:
detected. If fail to read it, it becomes undefined. It is recommended that a 16-bit
access instruction be used to read from TC1DRB.
after a value has been captured until the next edge is detected. So, the value
captured next will become “1” larger than the value captured right after capturing
starts.
ignore the first captured value.
CLR
LD
DI
SET
EI
LD
CPL
JRS
LD
LD
RETI
LD
LD
RETI
DW
HPULSE
(INTTC1SW). 0
(TC1CR), 00000110B
(EIRL). 5
(TC1CR), 00100110B
(INTTC1SW). 0
F, SINTTC1
A, (TC1DRBL)
W, (TC1DRBH)
L, (TC1DRBL)
H, (TC1DRBH)
PINTTC1
86FM48-74
WIDTH
7
[Hz])
;
;
;
;
;
;
;
;
;
;
INTTC1 service switch initial setting
Sets the TC1 mode and source clock
IMF = “0”
Enables INTTC1
IMF = “1”
Starts TC1 with an external trigger at
MCAP1 = 0
Inverts INTTC1 service switch
Reads TC1DRB (“H” level pulse width)
Reads TC1DRB (Period)
Duty calculation
TMP86FM48
2007-08-24