TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 38

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(2) Interrupt enable register (EIR)
(1) Interrupt latches (IL
When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. All interrupt latches are initialized to “0”
during reset.
Except for IL
(However, the read-modify-write instructions such as bit manipulation or operation
instructions cannot be used. Interrupt request would be cleared inadequately if interrupt is
requested while such instructions are executed.) Thus interrupt request can be
canceled/initialized by software.
the status for interrupt requests can be monitored by software.
except for the non-maskable interrupts (Software interrupt, undefined instruction
interrupt, address trap interrupt and watchdog interrupt). Non-maskable interrupt is
accepted regardless of the contents of the EIR.
enable flags (EF). These registers are located on address 002C
area, and they can be read and written by an instructions (Including read-modify-write
instructions such as bit manipulation or operation instructions).
Note: When manipulating IL, clear IMF (to disable interrupts) beforehand.
a.
An interrupt latch is provided for each interrupt source, except for a software interrupt.
The interrupt latches are located on address 002E
Interrupt latches are not set to “1” by an instruction. Since interrupt latches can be read,
The interrupt enable register (EIR) enables and disables the acceptance of interrupts,
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt
Interrupt master enable flag (IMF)
maskable-interrupt. While IMF = “0”, all maskable interrupts are not accepted
regardless of the status on each individual interrupt enable flag (EF). By setting IMF
to “1”, the interrupt becomes acceptable if the individuals are enabled. When an
interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked.
Thus the maskable interrupts which follow are disabled. By executing return interrupt
instruction [RETI/RETN], the stacked data, which was the status before interrupt
acceptance, is loaded on IMF again.
written by an instruction. The IMF is normally set and cleared by [EI] and [DI]
instruction respectively. During reset, the IMF is initialized to “0”, and maskable
interrupts are not accepted until it is set to “1”.
The interrupt enable register (IMF) enables and disables the acceptance of the whole
The IMF is located on bit0 in EIRL (Address: 003A
Example 1: Clears interrupt latches
Example 2: Reads interrupt latches
Example 3: Tests an interrupt latches
3
and IL
24
DI
LD
LDW
EI
LD
TEST
JR
to IL
2
, each latch can be cleared to “0” individually by instruction.
2
)
(ILE), 11110011B
(ILL), 1110100000111111B
WA, (ILL)
(IL).7
F, SSET
86FM48-34
H,
;
;
;
;
;
;
003C
IMF ← 0
IL
IL
IMF ← 1
W ← IL
IL
H
19
12
7
in SFR), and can be read and
= 1 then jump
, IL
, IL
H,
H
18
10
H
003A
and 003D
, A ← IL
← 0
to IL
6
H
← 0
L
and 003B
H
TMP86FM48
in SFR area.
2007-08-24
H
in SFR