TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 22

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

XOUT pin
STOP
Note: When the STOP mode is started with the EEPCR<MNPWDW> = “1”, the CPU wait for stabilizing of the power
pin
supply of Flash control circuit is executed after in the STOP warming-up time.
b.
NORMAL
operation
Example:
This is used in applications where a relatively short program is executed
repeatedly at periodic intervals. This periodic signal (For example, a clock from a
low-power consumption oscillator) is input to the
release mode, STOP mode is started even when the
Do not use any STOPx (x: 0 to 3) pin input for releasing STOP mode in
edge-sensitive release mode.
Note 1: Even if the
Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive
Edge-sensitive release mode (RELM = “0”)
Example 1: Starting STOP mode from NORMAL mode by testing a port P20.
SSTOPH:
Example 2: Starting STOP mode from NORMAL mode with an INT5 interrupt.
PINT5:
SINT5:
In this mode, STOP mode is released by a rising edge of the
not restarted.
mode, the release mode is not switched until a rising edge of the
input is detected.
Figure 1.4.8 Level-sensitive Release Mode
Starting STOP mode from NORMAL mode
LD
TEST
JRS
SET
TEST
JRS
LD
SET
RETI
LD
STOP operation
STOP
(SYSCR1), 01010000B
(P2PRD). 0
F, SSTOPH
(SYSCR1).7
(P2PRD). 0
F, SINT5
(SYSCR1), 01010000B
(SYSCR1). 7
(SYSCR1), 10010000B
86FM48-18
pin input is low after warming up start, the STOP mode is
STOP mode is released by the hardware.
Always released if the
input is high.
Warm-up
STOP
;
;
;
;
;
;
;
Only when EEPCR<MNPWDW> is “1”.
(The CPU wait period is added.)
Sets up the level-sensitive release mode
Wait until the
level
Starts STOP mode
To reject noise, STOP mode does not
start if port P20 is at high
Sets up the level-sensitive release mode.
Starts STOP mode
Starts after specified to the edge-sensitive
release mode
STOP
STOP
CPU wait
pin. In the edge-sensitive
period
pin input is high level.
STOP
STOP
pin
STOP
pin input goes low
TMP86FM48
NORMAL
operation
2007-08-24
pin input.
STOP
pin