TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 66

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.4.2
Watchdog Timer Control
watchdog timer is automatically enabled after reset.
(1) Malfunction detection methods using the watchdog timer
Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The
watchdog timer output will become active at the rising of an overflow from the binary
counters
WDTCR1<WDTOUT> = “1”, a reset is generated and the internal hardware is reseted.
When WDTCR1<WDTOUT> = “0”, a watchdog timer interrupt (INTWDT) is
generated.
IDLE mode, and automatically restarts (Continues counting) when the STOP/IDLE
mode is released.
Note: The watchdog timer consists of an internal divider and a two-stage binary counter.
1.
2.
The CPU malfunction is detected as follows.
If the CPU malfunctions such as endless looping or deadlock occur for any cause, the
The watchdog timer temporarily stops counting in STOP mode including warm-up or
Within 3/4 of
WDT detection
time
Within 3/4 of
WDT detection
time
Setting the detection time, selecting output, and clearing the binary counter.
Repeatedly clearing the binary counter within the setting detection time
Example: Sets the watchdog timer detection time to 2
SYSCR1
When clear code 4E
divider. Depending on the timing at which clear code 4E
register, the overflow time of the binary counter may be at minimum 3/4 of the time
set in WDTCR1 <WDTT>. Thus, write the clear code using a shorter cycle than 3/4
of the time set in WDTCR1 <WDTT>.
unless
LD
LD
LD
LD
LD
the
binary
H
(WDTCR2), 4EH
(WDTCR1), 00001101B
(WDTCR2), 4EH
(WDTCR2), 4EH
(WDTCR2), 4EH
86FM48-62
is written, only the binary counter is cleared, not the internal
counters
are
21
/fc [s] and resets the CPU malfunction.
;
;
;
;
;
cleared.
Clears the binary counters
WDTT ← 10, WDTOUT ← 1
Clears the binary counters (Always clear
immediately before and after changing
WDTT)
Clears the binary counters
Clears the binary counters
H
is written on the WDTCR2
At
this
TMP86FM48
time,
2007-08-24
when