TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 80

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(6) Programmable pulse generate (PPG) output mode
selected using two timer registers.
selected with the external trigger edge select bits (TC1CR<TC1S>) or on a command.
Its source clock is an internal clock. Once the timer starts running, the timer F/F1 is
inverted when the counter matches TC1DRB, generating the INTTC1 interrupt. The
counter keeps up-counting, and when counter matches TC1DRA, the timer F/F1 is
inverted, generating an INTTC1 interrupt. If TC1CR<MPPG1> was previously set to
“1” (One shot), TC1S is cleared to “00” automatically, causing the timer to stop. If
TC1CR<MPPG1> was previously cleared to “0” (Continuous pulse generation), the
counter is cleared, resulting in the counter keeping to run and the PPG output being
continued. If TC1CR<TC1S> is reset to “00” (One-shot-based automatic stop is
included) during PPG output, the P50 (
before the counter stops. In PPG output mode, set the output latch of port P50 to “1”.
The timer F/F1 is cleared to “0” at a reset. In addition, a positive or negative pulse can
be output because the output level can be set up at a start, using TC1CR<TFF1>. The
P50 (
write to TC1DRB unless the PPG output mode is set.
Note 1: To change the content of the timer register when the timer is running, change it to a
Note 2: Do not change TC1CR<TFF1> when the timer is running.
Note 3: In the PPG output mode, a value set in the timer register must satisfy: TC1DRA >
The PPG output mode is intended to output pulses having an arbitrary duty cycle
The timer starts at an edge (Rising or falling edge, that is, the same edge type as
Example: Pulse output “H” level 800 µs, “L” level 200 µs (at fc = 16 MHz, DV7CK = 0)
PPG
sufficiently large value, compared with the current count. If the timer register
content is changed to a value smaller than the current count when the timer is
running, it is likely that unintended pulses may be output.
TC1CR<TFF1> can be set correctly only at initialization (after a reset). When the
timer is stopped during PPG output, if the PPG output is at a logic state opposite to
the PPG that when the timer starts, it will become impossible to set TC1CR<TFF1>
correctly (An attempt to program TC1CR<TFF1> will cause a state opposite to the
programmed one to be set in the bit). Once the timer has stopped, putting the PPG
output securely on an arbitrary level requires initializing the timer F/F1. To initialize it,
put TC1CR<TC1M> in the timer mode again (It is unnecessary to start the timer
mode), and then put it in the PPG output mode again. At the same time, set
TC1CR<TFF1>.
TC1DRB
) pin outputs an inversion of the timer F/F1 output level. It is impossible to
SET
LD
LDW
LDW
LD
(P5DR). 0
(TC1CR), 10001011B
(TC1DRA), 07D0H
(TC1DRB), 0190H
(TC1CR), 10011011B
86FM48-76
PPG
) pin holds the same level that it does just
;
;
;
;
;
P50 output latch ← 1
Sets the PPG output mode
Sets the period (1 ms ÷ 2
Sets “L” level pulse width
(200 µs ÷ 2
Starts
3
/fc = 0190H)
TMP86FM48
3
/fc = 07D0H)
2007-08-24