TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 141

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

SIO1CR<SIOS>
SIO1SR<SIOF>
SIO1SR<SEF>
input
SO1 pin
SI1 pin
INTSIO1
interrupt
request
SIO1SR<TXF>
SIO1TDB
SIO1SR<RXF>
SIO1SR<RXERR>
SIO1RDB
SIO1CR<SIOINH>
SCK1
pin
Writing transmit
data A
A
Figure 2.13.19 Example of Transmit/Receive (Receive) Error Processing
A7
D7
Receive errors
Receive errors occur on the following situation. To protect SIO1RDB and the
shift
SIO1SR<RXERR> is “1”.
•
A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1
D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1
Start shift
operation
Shift operation is finished before reading out received data from
SIO1RDB at SIO1SR<RXF> is “1” in an external clock operation.
If receive error occurs, set the SIO1CR<SIOS> to “0” for reading the data
that received immediately before error occurence. And read the data
from SIO1RDB. Data in shift register (at errors occur) can be read by
reading the SIO1RDB again.
When SIO1SR<RXERR> is cleared to “0” after reading the received data,
SIO1SR<RXF> is cleared to “0”.
After clearing SIO1CR<SIOS> to “0”, when 8-bit serial clock is input to
confirm that SIO1SR<SIOF> is cleared to “0”.
If the received error occurs, set the SIO1CR<SIOINH> to “1” for stopping
the receive operation immediately. In this case, SIO1CR<SIOS>,
SIO1SR register, SIO1RDB register and SIO1TDB register are
initialized.
Note: If receive error is not corrected, an interrupt request does not
SCK1
register
Writing transmit
data B
pin, receive operation is stopped. To restart the receive operation,
generate after the error occurs.
Write a “0” after reading the received
data when a receive mode error occurs.
D
contents,
86FM48-137
B
Start shift
operation
the
Writing transmit
data C
Reading received
data D
received
B0
E0
C7
C
F7
Start shift
operation
C6 C5 C4 C3
F6 F5 F4 F3 F2 F1 F0
data
E
Reading received
data E
is
Unknown
FFH
ignored
TMP86FM48
2007-08-24
while
the