TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 114

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

SDA pin
SCL pin
(7) Start/stop condition generation
(8) Interrupt service request and cancel
condition
Start
Figure 2.12.7 Start Condition Generation and Slave Address Generation
to the SBIDBR are output on a bus after generating a start condition by writing “1” to
the MST, TRX, BB and PIN. It is necessary to set transmitted data to the SBIDBR and
set ACK to “1” beforehand.
to the MST, TRX and PIN, and “0” to the BB. Do not modify the contents of MST, TRX,
BB and PIN until a stop condition is generated on a bus.
level by another device, a stop condition is generated after releasing the SCL line.
The BB is set to “1” when a start condition on a bus is detected and is cleared to “0”
when a stop condition is detected.
of clocks set by the BC and the ACK is complete, a serial bus interface interrupt
request (INTSBI) is generated.
cleared to “0”. During the time that the PIN is “0”, the SCL pin is pulled-down to low
level.
be cleared to “0” by the program.
Note: If the arbitration lost occurs, when the slave address does not match, the PIN is not
When the BB (Bit5 in SBISR) is “0”, a slave address and a direction bit which are set
When the BB is “1”, sequence of generating a stop condition is started by writing “1”
When a stop condition is generated and the SCL line on a bus is pulled-down to low
The bus condition can be indicated by reading the contents of the BB (Bit5 in SBISR).
When a serial bus interface circuit is in the master mode and transferring a number
In the slave mode, the conditions of generating INTSBI are follows:
When a serial bus interface interrupt request occurs, the PIN (Bit4 in SBISR) is
Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to “1”.
The time from the PIN being set to “1” until the SCL pin is released takes t
Although the PIN (Bit4 in SBICRB) can be set to “1” by the program, the PIN can not
•
•
•
cleared to “0” even though INTSBI is generated.
At the end of acknowledge signal when the received slave address matches to
the value set by the I2CAR
At the end of acknowledge signal when a “GENERAL CALL” is received
At the end of transferring or receiving after matching of slave address or
receiving of “GENERAL CALL”
A6
1
Figure 2.12.8 Stop Condition Generation
SDA pin
SCL pin
A5
2
Slave address and the direction bit
A4
3
86FM48-110
A3
4
Stop condition
A2
5
A1
6
A0
7
R/
W
8
Acknowledge
signal
TMP86FM48
9
2007-08-24
LOW
.